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cool solutions for wireless connectivity xemics sa ? e-mail: info@xemics.com ? web: www.xemics.com datasheet xe88lc01/01a sensing machine data acquisition with zoomingadc xe88lc01/01a sensing machine data acquisition with 16+10 bit zoomingadc? general description the XE88LC01A is a data acquisition ultra low- power low-voltage system on a chip (soc) with a high efficiency embedded microcontroller unit (mcu), allowing for 1 mips at 300ua and 2.4 v, and multiplying in one clock cycle. the XE88LC01A includes a high resolution acquisition path with16+10 bits. the XE88LC01A is available with on chip rom or multiple-time-programm able (mtp) program memory. applications ? portable, battery operated instruments ? current loop powered instruments ? wheatstone bridge interfaces ? pressure and chemical sensors ? hvac control ? metering ? sports watches, wrist instruments key product features ? low-power, high resolution zoomingadc ? 0.5 to 1000 gain with offset cancellation ? up to 16 bits analog to digital converter ? up to 13 inputs multiplexer ? low-voltage low-power controller operation ? 2 mips with 2.4 v to 5.5 v operation ? 300 a at 1 mips over voltage range ? 22 kbyte (8 kinstruction) mtp ? 520 byte ram data memory ? rc and crystal oscillators ? 5 reset, 22 interrupt, 8 event sources ? 100 years mtp flash retention at 55c ordering information product temperature range memory type package xe88lc01mi027* -40c to 85 c mtp lqfp44 XE88LC01Ami000 -40c to 85 c mtp die XE88LC01Ami027 -40c to 85 c mtp lqfp44 XE88LC01Are000 -40c to 125 c rom die XE88LC01Are027 -40c to 125 c rom lqfp44 *not for new designs
d0304-60 datasheet xe88lc01/01a sensing machine data acquisition with zoomingadc table of contents chapter 1 xe88lc01/01a overview chapter 2 xe88lc01/01a performance chapter 3 xe88lc01/01a cpu chapter 4 xe88lc01/01a memory chapter 5 system block chapter 6 reset generator chapter 7 clock generation chapter 8 interrupt handler chapter 9 event handler chapter 10 low power ram chapter 11 port a chapter 12 port b chapter 13 port c chapter 14 universal asynchronous receiver/transmitter (uart) chapter 15 universal synchronous receiver/transmitter (usrt) chapter 16 acquisition chain chapter 17 voltage multiplier chapter 18 counters/timers/pwm chapter 19 the voltage level detector chapter 20 xe88lc01/01a dimensions
1-1 lc01 - 1.2 ? 24 avril 2003 d0304-60 datasheet xe88lc01 / 01a 1. general overview contents 1.1 top schematic 1-2 1.1.1 general description 1-2 1.1.2 xe88lc01 vs XE88LC01A 1-4 1.2 pin map 1-4 1.2.1 bare die 1-4 1.2.2 lqfp-44 package 1-5 1.3 pin assignment 1-6
1-2 d0304-60 datasheet xe88lc01 / 01a 1.1 top schematic 1.1.1 general description the top level block schematic of the circuit is shown in figure 1-1. the heart of the circuit consists of the coolrisc816? cpu core. this core includes an 8x8 multiplier and 16 internal registers. the bus controller generates all control signals for access to all data registers other than the cpu internal registers. the reset block generates the adequate reset signals for t he rest of the circuit as a function of the set- up contained in its control registers. possible re set sources are the power-on-reset (por), the external pin reset, the watchdog (wd), a bus error detected by the bus controller or a programmable pattern on port a. differ ent low power modes are implemented. the clock generation and power management block se ts up the clock signals and generates internal supplies for different blocks. the clock can be gener ated from the rc oscillator (this is the start-up condition), the crystal oscillator (xtal) or an ex ternal clock source (given on the oscin pin). the test controller generates all set-up signals for diffe rent test modes. in normal operation, it is used as a set of 8 low power data registers. if power consumption is important for the application, the variables that need to be accessed very often should be stored in these registers rather than in the ram. the irq handler routes the interrupt signals of the different peripherals to t he irq inputs of the cpu core. it allows masking of the interrupt sources and it flags which interrupt source is active. events are generally used to restart the processor a fter a halt period without jumping to a specified address, i.e. the program executi on resumes with the instruction fo llowing the halt instruction. the evn handler routes the event signals of the different peripherals to t he evn inputs of the cpu core. it allows masking of the interrupt sources and it flags which interrupt source is active. the port b is an 8 bit parallel io port with anal og capabilities. the urst, uart, and pwm block also make use of this port. the instruction memory is a 22-bit wide flash or rom memory depending on the circuit version. flash and rom versions have both 8k instruction memory. the data memory on this product is a 512 byte sram. the acquisition chain is a high resolution ac quisition path with the 16+10 bits zoomingadc ? . the vmult (voltage multiplier) powers a part of the acquisition chain. port a is an 8 bit parallel input port. it can also gener ate interrupts, events or a reset. it can be used to input external clocks for t he timer/counter/pwm block. port c is a general purpose 8 bit parallel i/o port. the usrt (universal synchronous receiver/transmitte r) contains some simple hardware functions in order to simplify the software implement ation of a synchronous serial link. the uart (universal asynchronous receiver/transmi tter) contains a full hardware implementation of the asynchronous serial link. the counters/timers/pwm can take its clocks from in ternal or external sources (on port a) and can generate interrupts or events. t he pwm is output on port b.
1-3 d0304-60 datasheet xe88lc01 / 01a the vld (voltage level detector) detects the batte ry end of life with respect to a programmable threshold. instruction memory b u s c o n t r o l l e r test controller reset block wd clock generation/ power management vreg xtal rc cpu coolrisc816 8 x 8 multiplier 16 cpu registers irq handling evn handling port b 8 data registers port a usrt port c address control datain dataout reset control clocks test control irq evn vpp/test vbat vss reset oscin oscout vreg pb(7:0) pa(7:0) pc(7:0) ac_r(3:0) ac_a(7:0) vmult data memory uart counters timers pwm vld pb(5:4) pb(7:6) pa(3:0) pb(1:0) por acquisition chain zoomingadc vmult figure 1-1. block schematic of the xe88lc01/01a circuit.
1-4 d0304-60 datasheet xe88lc01 / 01a 1.1.2 xe88lc01 vs XE88LC01A the XE88LC01A has a new reset pin function. t he action of the reset pin of the XE88LC01A resets the clock registers too and creates an additi onal short delay. see the reset chapter for more information. 1.2 pin map 1.2.1 bare die (52.6,4075.5) pa(4) (52.6, 3795.5) pa(5) (52.6,3515.5) vbat (52.6, 3235.5) pa(6) (52.6, 2955.5) pa(7) (52.6, 2675.5) pc(0) (52.6, 2395.5) pc(1) (52.6, 2115.5) pc(2) (52.6, 1835.5) pc(3) (52.6, 1555.5) vss (52.6, 1275.5) pc(4) (52.6, 995.5) pc(5) (52.6, 715.5) pc(6) (52.6, 435.5) pc(7) vss (3958.4, 3657.4) ac_r(0) (3958.4, 3657.4) ac_r(1) (3958.4, 3372.4) ac_a(0) (3958.4, 3087.4) ac_a(1) (3958.4, 2802.4) vss (3958.4, 2517.4) ac_a(2) (3958.4, 2232.4) ac_a(3) (3958.4, 1947.4) ac_a(4) (3958.4,1662.4) ac_a(5) (3958.4, 1377.4) ac_a(6) (3958.4, 1092.4) vbat (3958.4, 807.4) ac_a(7) (3958.4, 522.4) pa(3) ( 417.6, 4453.4) pa(2) ( 682.6, 4453.4) pa(1) ( 947.6, 4453.4) pa(0) (1212.6, 4453.4) oscout (1477.6, 4453.4) vss (1742.6, 4453.4) oscin (2007.6, 4453.4) vmult (2537.0, 4453.4) reset (2802.6, 4453.4) vreg (3067.6, 4453.4) vss (3332.6, 4453.4) vbat (3597.6, 4453.4) ( 398.5, 47.6) pb(0) ( 533.5, 47.6) pb(1) ( 668.5, 47.6) pb(2) ( 798.5, 47.6) pb(3) ( 933.5, 47.6) pb(4) (1063.5, 47.6) vbat (1198.5, 47.6) pb(5) (1328.5, 47.6) pb(6) (1463.5, 47.6) pb(7) (1934.1, 47.6) test (2394.1, 47.6) vss (2854.1, 47.6) ac_r(3) (2854.1, 47.6) ac_r(2) 4100 4600 figure 1-2. die dimensions and pin coordinates (in m).
1-5 d0304-60 datasheet xe88lc01 / 01a 1.2.2 lqfp-44 package the xe88lc01/01a is delivered in a lqfp- 44 package. the pin map is given below. 10 5 1 pc(7) pc(6) pc(5) pc(4) pc(3) pc(2) pc(1) pc(0) pa(7) pa(6) pa(5) ac_a(7) ac_a(6) ac_a(5) ac_a(4) ac_a(3) ac_a(2) ac_a(1) ac_a(0) ac_r(1) ac_r(0) vss vbat vreg reset vmult oscin oscout pa(0) pa(1) pa(2) pa(3) pa(4) ac_r(2) ac_r(3) vpp/test pb(7) pb(6) pb(5) pb(4) pb(3) pb(2) pb(1) pb(0) 25 30 20 15 35 40 figure 1-3. lqfp-44 pin map package pin name package pin name 1 pa(5) 23 ac_a(7) 2 pa(6) 24 ac_a(6) 3 pa(7) 25 ac_a(5) 4 pc(0) 26 ac_a(4) 5 pc(1) 27 ac_a(3) 6 pc(2) 28 ac_a(2) 7 pc(3) 29 ac_a(1) 8 pc(4) 30 ac_a(0) 9 pc(5) 31 ac_r(1) 10 pc(6) 32 ac_r(0) 11 pc(7) 33 vss 12 pb(0) 34 vbat 13 pb(1) 35 vreg 14 pb(2) 36 reset 15 pb(3) 37 vmult 16 pb(4) 38 oscin 17 pb(5) 39 oscout 18 pb(6) 40 pa(0) 19 pb(7) 41 pa(1) 20 vpp/test 42 pa(2) 21 ac_r(3) 43 pa(3) 22 ac_r(2) 44 pa(4) table 1-1. bonding plan of the lqfp- 44 package (lqfp 44l 10x10mm thick 1.6 mm)
1-6 d0304-60 datasheet xe88lc01 / 01a 1.3 pin assignment the table below gives a short descripti on of the different pin assignments. pin assignment vbat positive power supply vss negative power supply vreg connection for the mandatory external capacitor of t he voltage regulator vpp/test high voltage supply for flash memory programming (nc in rom versions) reset resets the circuit when the voltage is high oscin/oscout quartz crystal connections, also used for flash memory programming pa(7:0) parallel input port a pins pb(7:0) parallel i/o port b pins pc(7:0) parallel i/o port c pins ac_a(7:0) acquisition chain input pins ac_r(3:0) acquisition chain reference pins vmult connection for the external capacitor if vbat is below 3v table 1-2. pin assignment table 1-3 gives a more detailed pin map for the di fferent pins. it also indicates the possible i/o configuration of these pins. the indications in bl ue bold are the configurati on at start-up. the pins cntx pins are possible counter inputs, pwmx are possible pwm outputs. pin function i/o configuration lqfp-44 first second third ai ao di do od pu power 1 pa(5) x x 2 pa(6) x x 3 pa(7) x x 4 pc(0) x x 5 pc(1) x x 6 pc(2) x x 7 pc(3) x x 8 pc(4) x x 9 pc(5) x x 10 pc(6) x x 11 pc(7) x x 12 pb(0) pwm0 x x x x x x 13 pb(1) pwm1 x x x x x x 14 pb(2) x x x x x x 15 pb(3) x x x x x x 16 pb(4) usrt_s0 x x x x x x 17 pb(5) usrt_s1 x x x x x x 18 pb(6) uart_tx x x x x x x 19 pb(7) uart_rx x x x x x x 20 vpp test x 21 ac_r(3) x 22 ac_r(2) x 23 ac_a(7) x 24 ac_a(6) x 25 ac_a(5) x 26 ac_a(4) x 27 ac_a(3) x
1-7 d0304-60 datasheet xe88lc01 / 01a 28 ac_a(2) x 29 ac_a(1) x 30 ac_a(0) x 31 ac_r(1) x 32 ac_r(0) x 33 vss x 34 vbat x 35 vreg x 36 reset x 37 vmult x 38 oscin x 39 oscout x 40 pa(0) cnta x x 41 pa(1) cntb x x 42 pa(2) cntc x x 43 pa(3) cntd x x 44 pa(4) x x pin map table legend: blue bold: configuration at start up ai: analog input ao: analog output di: digital input do: digital output od: nmos open drain output pu: pull-up resistor power: power supply table 1-3. pin description table
2-1 lc01 - 1.0 ? 08 october 2002 d0304-60 datasheet xe88lc01/01a 2 xe88lc01/01a performance 2.1 absolute maximum ratings 2-2 2.2 operating range 2-2 2.3 supply configurations 2-3 2.3.1 flash circuit 2-3 2.3.2 rom circuit 2-3 2.4 current consumption 2-5 2.5 operating speed 2-6 2.5.1 flash version 2-6 2.5.2 rom circuit version 2-6
2-2 d0304-60 datasheet xe88lc01/01a 2.1 absolute maximum ratings table 2-1. absolute maximal ratings min. max. note voltage applied to vbat with respect to vss -0.3 6.0 v voltage applied to vpp with respect to vss vbat-0.3 12 v voltage applied to all pins except vpp and vbat vss-0.3 vbat+0.3 v storage temperature (rom device or unprogrammed flash device) -55 150 c storage temperature (programmed flash device) -40 85 c stresses beyond the absolute maximal ratings may cause permanent damage to the device. functional operation at the absolute maximal ratings is not implied. exposure to conditions beyond the absolute maximal ratings may affe ct the reliability of the device. 2.2 operating range table 2-2. operating range for the flash device min. max. note voltage applied to vbat with respect to vss 2.4 5.5 v voltage applied to vbat with respect to vss during the flash programming 3.3 5.5 v 1 voltage applied to vpp with respect to vss vbat 11.5 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 85 c capacitor on vreg (flash version) 0.8 1.2 f 2 capacitor on vmult 1.0 3.0 nf 3 1. during the programming of the device, t he supply voltage should at least be equal to the supply voltage used during normal operation. 2. the capacitor on vreg is mandatory. 3. the capacitor on vmult is optional. the capac itor has to be present if the multiplier is enabled. the multiplier has to be enabled if vbat<3.0v. table 2-3. operating range for the rom device min. max. note voltage applied to vbat with respect to vss 2.4 5.5 v voltage applied to all pins except vpp and vbat vss vbat v operating temperature range -40 125 c capacitor on vreg 0.1 1.2 f 1 capacitor on vmult 1.0 3.0 nf 2 1. the capacitor may be omitt ed when vreg is connected to vbat. 2. the capacitor on vmult is optional. the capac itor has to be present if the multiplier is enabled. the multiplier has to be enabled if vbat<3.0v. all specifications in this document are valid for the complete operating range unless otherwise specified.
2-3 d0304-60 datasheet xe88lc01/01a table 2-4. operating range of the flash memory min. max. note retention time at 85c 10 years 1 retention time at 55c 100 years 1 number of programming cycles 10 2 1. valid only if programmed using a programming tool that is qualified 2. circuits can be programmed more than 10 times but in that case, the retention time is no longer guaranteed. 2.3 supply configurations 2.3.1 flash circuit the flash version of the circuit can be run from a supply between 2.4v and 5.5v (figure 2-1). the capacitor on vreg has to be connected at all times (value in table 2-2) to guarantee proper operation of the device. the capacitor on vmult is only required if the circuit is to be operated below 3v. vbat vreg vmult vss 2.4v ? 5.5v c vreg c vmult figure 2-1. supply configuration for the flash circuit. 2.3.2 rom circuit for the rom version, two possible operating modes exist: with and without voltage regulator. using the voltage regulator, low power consumption w ill be obtained even with supply voltages above 2.4v. without the voltage regulator (i.e. vreg short-ci rcuited to vbat), a higher speed can be obtained. 2.1.3.1 low power operation in this case, the internal voltage regulator is us ed in order to maintain a low power consumption independent from the supply voltage. the capacitor on vreg has to be connected at all times (value in table 2-3) to guarantee proper operation of the device. the capacitor on vmult has to be connected only when vbat<3v.
2-4 d0304-60 datasheet xe88lc01/01a vbat vreg vmult vss 2.4v ? 5.5v c vreg c vmult figure 2-2. supply voltage connections for lo w power operation of the rom version. 2.1.3.2 high speed operation in this case, the internal voltage regulator is not used. the operation speed of the circuit can be increased with increasing supply voltage but the suppl y current will also increase. the capacitor on vmult has to be connected only when vbat<3v. in this case, the supply voltage can decrease down to 2.15v. beware however that the zoomingadc tm will not run below 2.4v (see figure 2-4). in this configuration, the circ uit can not be used above 3.3v. vbat vreg vmult vss 2.15v ? 3.3v c vmult figure 2-3. supply voltage connections for high speed operation of the rom version.
2-5 d0304-60 datasheet xe88lc01/01a 0 2.15 2.4 3.3 vbat (v) cpu parallel and serial ports rc and crystal oscillator vld counters and pwm acquisition chain voltage multiplier figure 2-4. operation range of the different circuit blocks 2.4 current consumption the tables below give the current consumption for t he circuit in different configurations. the figures are indicative only and may change as a function of the actual software implemented in the circuit. table 2-5 gives the current consumption for the flash version of the circuit. the peripherals are disabled. the parallel ports a and b are configured in input with pull up, the parallel port c is configured as an output. their pins are not connect ed externally. the pin reset is connected to vss and the pin vpp/test is connected to vbat. he input s of the acquisition chain are connected to vss. table 2-5. typical current consumption of the xe88lc01m version (8k instructions flash memory) operation mode cpu rc xtal consumption comments note high speed cpu 1 mips 1 mhz off 310 a 2.4v<>5.5v, 27 c low power cpu 32 kips off 32 khz 10 a 2.4v <>5.5v, 27 c low power time keeping halt off 32 khz 1.0 a 2.4v <>5.5v, 27 c fast wake-up time keeping halt ready 32khz 1.7 a 2.4v <>5.5v, 27 c immediate wake- up time keeping halt 100 khz off 1.4 a 2.4v <>5.5v, 27 c vld static current 15 a 2.4v <>5.5v, 27 c 16 bit resolution data acquisition halt 2 mhz off 190 a 3.0v, 27 c 1 12 bit , gain 100, data acquisition halt 2 mhz off 460 a 3.0v, 27 c 2 1. pga disabled, adc enabled, 16 bit resolution 2. pga 1 disabled, pga 2 and 3 enabled, adc enabled, 12 bit resolution for more information concerning the cu rrent consumption of the zoomingadc tm , see the chapter power consumption in the acquisition chain document ation which shows the current consumption of this block as a function of temperature and volt age and for different configurations of the pga and adc. the power consumption of the rom version of the circ uit is identical if it is configured as shown in figure 2-2. in the high speed configuration, the current consumption will increase proportional with vbat.
2-6 d0304-60 datasheet xe88lc01/01a 2.5 operating speed 2.5.1 flash version the speed of the devices is not highly dependent upon the supply voltage. however, by limiting the temperature range, the speed can be increased. t he minimal guaranteed speed as a function of the supply voltage and maximal temperature operati ng temperature is given in figure 2-5. 0 1 2 3 4 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c figure 2-5. guaranteed speed as a function of the supply voltage and maximal temperature. 2.5.2 rom circuit version 2.1.5.1 low power supply configuration in the low power supply configuration as show n in figure 2-2, the operating speed does not depend highly on the supply voltage as shown in figure 2-6. 0 0.5 1 1.5 2 2.5 3 3.5 22.533.544.555.5 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-6. guaranteed speed as a function of suppl y voltage and for different maximal temperatures using the voltage regulator. 2.1.5.2 high speed supply configuration in the high speed supply configuration of figure 2- 3, the guaranteed speed of the circuit is shown in figure 2-7.
2-7 d0304-60 datasheet xe88lc01/01a 0 1 2 3 4 2 2.2 2.4 2.6 2.8 3 3.2 3.4 supply voltage vbat (v) speed (mips) 85c 45c 125c figure 2-7. guaranteed speed as a function of s upply voltage and for three temperature ranges when vreg=vbat.
3-1 d0304-60 datasheet xe88lc01/01a 3. cpu contents 3.1 cpu description 3-2 3.2 cpu internal registers 3-2 3.3 cpu instruction short reference 3-4
3-2 d0304-60 datasheet xe88lc01/01a 3.1 cpu description the cpu of the xe8000 series is a low power risc core. it has 16 internal registers for efficient implementation of the c compiler. its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. all instructi ons are executed in one clock cycle, including conditional jumps and 8x8 multiplication. the circui t therefore runs on 1 mips on a 1mhz clock. the cpu hardware and software description is gi ven in the document ?coolrisc816 hardware and software reference manual?. a short summa ry is given in the following paragraphs. the good code efficiency of the cpu core make s it possible to compute a polynomial like y b b x y a a z ? + + ? ? + = 1 0 1 0 ) ( in less than 300 clock cycles (software code generated by the xemics c-compiler, all numbers are signed integers on 16 bits). 3.2 cpu internal registers as shown in figure 3-1, the cpu has 16 internal 8-bit registers. some of these registers can be concatenated to a 16-bit word for use in some instru ctions. the function of these registers is defined in table 3-1. the status register stat (table 3-2) is used to m anage the different interrupt and event levels. an interrupt or an event can both be used to wake up after a halt instruction. the difference is that an interrupt jumps to a special interrupt function whereas an event continues the software execution with the instruction fo llowing the halt instruction. the program counter (pc) is a 16 bit register that indicates the address of the instruction that has to be executed. the stack (st n ) is used to memorise the return address when executing subroutines or interrupt routines. instruction memory 22bit cpu cpu internal registers a stat iph ipl i3h i3l i2h i2l i1h i1l i0h i0l r3 r2 r1 r0 data memory data bus instruction bus pc st 1 st 2 st 3 st 4 program counter stack figure 3-1. cpu internal registers
3-3 d0304-60 datasheet xe88lc01/01a register name register function r0 general purpose r1 general purpose r2 general purpose r3 data memory offset i0h msb of the data memory index i0 i0l lbs of the data memory index i0 i1h msb of the data memory index i1 i1l lbs of the data memory index i1 i2h msb of the data memory index i2 i2l lbs of the data memory index i2 i3h msb of the data memory index i3 i3l lbs of the data memory index i3 iph msb of the program memory index ip ipl lbs of the program memory index ip stat status register a accumulator table 3-1. cpu internal register definition bit name function 7 ie2 enables (when 1) the interrupt request of level 2 6 ie1 enables (when 1) the interrupt request of level 1 5 gie enables (when 1) all interrupt request levels 4 in2 interrupt request of level 2. the interr upts labelled ?low? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 3 in1 interrupt request of level 1. the interr upts labelled ?mid? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 2 in0 interrupt request of level 0. the interr upts labelled ?hig? in the interrupt handler are routed to this interrupt level. this bit has to be cleared when the interrupt is served. 1 ev1 event request of level 1. the events labe lled ?low? in the event handler are routed to this event level. this bit has to be cleared when the event is served. 0 ev0 event request of level 1. the events labe lled ?hig? in the event handler are routed to this event level. this bit has to be cleared when the event is served. table 3-2. status register description the cpu also has a number of flags that can be used for conditional jumps. these flags are defined in table 3-3. symbol name function z zero z=1 when the accumulator a content is zero c carry this flag is used in sh ift or arithmetic operations. for a shift operation, it has the value of the bit that was shifted out (lsb for shift right, msb for shift left). for an arithmetic operation with unsigned numbers: it is 1 at occurrence of an overfl ow during an addition (or equivalent). it is 0 at occurrence of an underflow during a subtraction (or equivalent). v overflow this flag is used in shift or arithmetic operations. for arithmetic or shift operations with signed numbers, it is 1 if an overflow or underflow occurs. table 3-3. flag description
3-4 d0304-60 datasheet xe88lc01/01a 3.3 cpu instruction short reference table 3-4 shows a short description of the different instructions availabl e on the coolrisc816. the notation cc in the conditional jump instruction refers to the condition description as given in table 3-6. the notation reg, reg1, reg2, reg3 refers to one of the cpu inter nal registers of table 3-1. the notation eaddr and dm(eaddr) refer to one of the extended address modes as defined in table 3-5. the notation dm(xxx) refers to the data memory location with address xxx. instruction modification operation jump addr[15:0] -,-,-, - pc := addr[15:0] jump ip -,-,-, - pc := ip j cc addr[15:0] -,-,-, - if cc is true then pc := addr[15:0] j cc ip -,-,-, - if cc is true then pc := ip call addr[15:0] -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := addr[15:0] call ip -,-,-, - st n+1 := st n (n>1); st 1 := pc+1; pc := ip calls addr[15:0] -,-,-, - ip := pc+1; pc := addr[15:0] calls ip -,-,-, - ip := pc+1; pc := ip ret -,-,-, - pc := st 1 ; st n := st n+1 (n>1) rets -,-,-, - pc := ip reti -,-,-, - pc := st 1 ; st n := st n+1 (n>1); gie :=1 push -,-,-, - pc := pc+1; st n+1 := st n (n>1); st 1 := ip pop -,-,-, - pc := pc+1; ip := st 1 ; st n := st n+1 (n>1) move reg ,#data[7:0] -,-, z, a a := data[7:0]; reg := data[7:0] move reg1 , reg2 -,-, z, a a := reg2 ; reg1 := reg2 move reg , eaddr -,-, z, a a := dm(eaddr) ; reg := dm(eaddr) move eaddr , reg -,-,-, - dm(eaddr) := reg move addr[7:0],#data[7:0] -,-,-, - dm(addr[7:0]) := data[7:0] cmvd reg1 , reg2 -,-, z, a a := reg2 ; if c=0 then reg1 := a; cmvd reg , eaddr -,-, z, a a := dm(eaddr) ; if c=0 then reg := a cmvs reg1 , reg2 -,-, z, a a := reg2 ; if c=1 then reg1 := a; cmvs reg , eaddr -,-, z, a a := dm(eaddr) ; if c=1 then reg := a shl reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := 0; c := reg2[7] ; reg1 := a shl reg c, v, z, a a := reg <<1; a[0] := 0; c := reg[7] ; reg := a shl reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] ; reg := a shlc reg1 , reg2 c, v, z, a a := reg2 <<1; a[0] := c; c := reg2[7] ; reg1 := a shlc reg c, v, z, a a := reg <<1; a[0] := c; c := reg[7] ; reg := a shlc reg , eaddr c, v, z, a a := dm(eaddr) <<1; a[0] := c; c := dm(eaddr)[7] ; reg := a shr reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := 0; c := reg2[0] ; reg1 :=a shr reg c, v, z, a a := reg >>1; a[7] := 0; c := reg[0] ; reg := a shr reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := 0; c := dm(eaddr)[0] ; reg := a shrc reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := c; c := reg2[0] ; reg1 := a shrc reg c, v, z, a a := reg >>1; a[7] := c; c := reg[0] ; reg := a shrc reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := c; c := dm(eaddr)[0] ; reg := a shra reg1 , reg2 c, v, z, a a := reg2 >>1; a[7] := reg2[7] ; c := reg2[0] ; reg1 := a shra reg c, v, z, a a := reg >>1; a[7] := reg[7] ; c := reg[0] ; reg := a shra reg , eaddr c, v, z, a a := dm(eaddr) >>1; a[7] := dm(eaddr)[7] ; c := dm(eaddr)[0] ; reg := a cpl1 reg1 , reg2 -,-, z, a a := not( reg2 ); reg1 := a cpl1 reg -,-, z, a a := not( reg ); reg := a cpl1 reg , eaddr -,-, z, a a := not( dm(eaddr) ); reg := a cpl2 reg1 , reg2 c, v, z, a a := not( reg2 )+1; if a=0 then c:=1 else c := 0; reg1 := a cpl2 reg c, v, z, a a := not( reg )+1; if a=0 then c:=1 else c := 0; reg := a cpl2 reg , eaddr c, v, z, a a := not( dm(eaddr) )+1; if a=0 then c:=1 else c := 0; reg := a cpl2c reg1 , reg2 c, v, z, a a := not( reg2 )+c; if a=0 and c=1 then c:=1 else c := 0; reg1 := a cpl2c reg c, v, z, a a := not( reg )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a cpl2c reg , eaddr c, v, z, a a := not( dm(eaddr) )+c; if a=0 and c=1 then c:=1 else c := 0; reg := a inc reg1 , reg2 c, v, z, a a := reg2 +1; if a=0 then c := 1 else c := 0; reg1 := a inc reg c, v, z, a a := reg +1; if a=0 then c := 1 else c := 0; reg := a inc reg , eaddr c, v, z, a a := dm(eaadr) +1; if a=0 then c := 1 else c := 0; reg := a incc reg1 , reg2 c, v, z, a a := reg2 +c; if a=0 and c=1 then c := 1 else c := 0; reg1 := a incc reg c, v, z, a a := reg +c; if a=0 and c=1 then c := 1 else c := 0; reg := a incc reg , eaddr c, v, z, a a := dm(eaadr) +c; if a=0 and c=1 then c := 1 else c := 0; reg := a dec reg1 , reg2 c, v, z, a a := reg2 -1; if a=hff then c := 0 else c := 1; reg1 := a
3-5 d0304-60 datasheet xe88lc01/01a dec reg c, v, z, a a := reg -1; if a=hff then c := 0 else c := 1; reg := a dec reg , eaddr c, v, z, a a := dm(eaddr) -1; if a=hff then c := 0 else c := 1; reg := a decc reg1 , reg2 c, v, z, a a := reg2 -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg1 := a decc reg c, v, z, a a := reg -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a decc reg , eaddr c, v, z, a a := dm(eaddr) -(1-c); if a=hff and c=0 then c := 0 else c := 1; reg := a and reg ,#data[7:0] -,-, z, a a := reg and data[7:0]; reg := a and reg1 , reg2 , reg3 -,-, z, a a := reg2 and reg3 ; reg1 := a and reg1 , reg2 -,-, z, a a := reg1 and reg2 ; reg1 := a and reg , eaddr -,-, z, a a := reg and dm(eaddr) ; reg := a or reg ,#data[7:0] -,-, z, a a := reg or data[7:0]; reg := a or reg1 , reg2 , reg3 -,-, z, a a := reg2 or reg3 ; reg1 := a or reg1 , reg2 -,-, z, a a := reg1 or reg2 ; reg1 := a or reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a xor reg ,#data[7:0] -,-, z, a a := reg xor data[7:0]; reg := a xor reg1 , reg2 , reg3 -,-, z, a a := reg2 xor reg3 ; reg1 := a xor reg1 , reg2 -,-, z, a a := reg1 xor reg2 ; reg1 := a xor reg , eaddr -,-, z, a a := reg or dm(eaddr) ; reg := a add reg ,#data[7:0] c, v, z, a a := reg +data[7:0]; if overflow then c:=1 else c := 0; reg := a add reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 ; if overflow then c:=1 else c := 0; reg1 := a add reg1 , reg2 c, v, z, a a := reg1 + reg2 ; if overflow then c:=1 else c := 0; reg1 := a add reg , eaddr c, v, z, a a := reg + dm(eaddr) ; if overflow then c:=1 else c := 0; reg := a addc reg ,#data[7:0] c, v, z, a a := reg +data[7:0]+c; if overflow then c:=1 else c := 0; reg := a addc reg1 , reg2 , reg3 c, v, z, a a := reg2 + reg3 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg1 , reg2 c, v, z, a a := reg1 + reg2 +c; if overflow then c:=1 else c := 0; reg1 := a addc reg , eaddr c, v, z, a a := reg + dm(eaddr) +c; if overflow then c:=1 else c := 0; reg := a subd reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c := 0 else c := 1; reg := a subd reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 ; if underflow then c := 0 else c := 1; reg1 := a subd reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c := 0 else c := 1; reg1 := a subd reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c := 0 else c := 1; reg := a subdc reg ,#data[7:0] c, v, z, a a := data[7:0]- reg -(1-c); if underflow then c := 0 else c := 1; reg := a subdc reg1 , reg2 , reg3 c, v, z, a a := reg2 - reg3 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg1 , reg2 c, v, z, a a := reg2 - reg1 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subdc reg , eaddr c, v, z, a a := dm(eaddr) - reg -(1-c); if underflow then c := 0 else c := 1; reg := a subs reg ,#data[7:0] c, v, z, a a := reg -data[7:0]; if underflow then c := 0 else c := 1; reg := a subs reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg1 , reg2 c, v, z, a a := reg1 - reg2 ; if underflow then c := 0 else c := 1; reg1 := a subs reg , eaddr c, v, z, a a := reg - dm(eaddr) ; if underflow then c := 0 else c := 1; reg := a subsc reg ,#data[7:0] c, v, z, a a := reg -data[7:0]-(1-c); if underflow then c := 0 else c := 1; reg := a subsc reg1 , reg2 , reg3 c, v, z, a a := reg3 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg1 , reg2 c, v, z, a a := reg1 - reg2 -(1-c); if underflow then c := 0 else c := 1; reg1 := a subsc reg , eaddr c, v, z, a a := reg - dm(eaddr) -(1-c); if underflow then c := 0 else c := 1; reg := a mul reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mul reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mul reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mul reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mula reg ,#data[7:0] u, u, u, a a := (data[7:0]* reg )[7:0]; reg := (data[7:0]* reg )[15:8] mula reg1 , reg2 , reg3 u, u, u, a a := ( reg2 * reg3 )[7:0]; reg1 := ( reg2 * reg3 )[15:8] mula reg1 , reg2 u, u, u, a a := ( reg2 * reg1 )[7:0]; reg1 := ( reg2 * reg1 )[15:8] mula reg , eaddr u, u, u, a a := ( dm(eaddr) * reg )[7:0]; reg := ( dm(eaddr) * reg )[15:8] mshl reg ,#shift[2:0] u, u, u, a a := ( reg *2 shift )[7:0]; reg := ( reg *2 shift )[15:8] mshr reg ,#shift[2:0] u, u, u, a a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] mshra reg ,#shift[2:0] u, u, u, a* a := ( reg *2 (8-shift )[7:0]; reg := ( reg *2 (8-shift )[15:8] cmp reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmp reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg ,#data[7:0] c, v, z, a a := data[7:0]- reg ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg1 , reg2 c, v, z, a a := reg2 - reg1 ; if underflow then c :=0 else c:=1; v := c and (not z) cmpa reg , eaddr c, v, z, a a := dm(eaddr) - reg ; if underflow then c :=0 else c:=1; v := c and (not z) tstb reg ,#bit[2:0] -, -, z, a a[bit] := reg[bit] ; other bits in a are 0 setb reg ,#bit[2:0] -, -, z, a reg[bit] := 1; other bits unchanged; a := reg clrb reg ,#bit[2:0] -, -, z, a reg[bit] := 0; other bits unchanged; a := reg invb reg ,#bit[2:0] -, -, z, a reg[bit] := not reg[bit] ; other bits unchanged; a := reg
3-6 d0304-60 datasheet xe88lc01/01a sflag -,-,-, a a[7] := c; a[6] := c xor v; a[5] := st full; a[4] := st empty rflag reg c, v, z, a a := reg << 1; ; a[0] := 0; c := reg[7] rflag eaddr c, v, z, a a := dm(eaddr) <<1; a[0] :=0; c := dm(eaddr)[7] freq divn -,-,-, - reduces the cpu fr equency (divn=nodiv, div2, div4, div8, div16) halt -,-,-, - halts the cpu nop -,-,-, - no operation - = unchanged, u = undefined, *mshr reg ,# 1 doesn?t shift by 1 table 3-4. instruction short reference the coolrisc816 has 8 different addressing modes. thes e modes are described in table 3-5. in this table, the notation ix refers to one of the data memory index registers i0, i1, i2 or i3. using eaddr in an instruction of table 3-4 will acce ss the data memory at the address dm(eaddr) and will simultaneously execute the index operation. extended address eaddr accessed data memory location dm(eaddr) index operation addr[7:0] dm(h00&addr[7:0]) - direct addressing (ix) dm(ix) - indexed addressing (ix, offset[7:0]) dm(ix+offset) - indexed addressing with immediate offset (ix,r3) dm(ix+r3) - indexed addressing with register offset (ix)+ dm(ix) ix := ix+1 indexed addressing with index post-increment (ix,offset[7:0])+ dm(ix+offset) ix := ix+offset indexed addressing with index post-increment by the offset -(ix) dm(ix-1) ix := ix-1 indexed addressing with index pre-decrement -(ix,offset[7:0]) dm(ix-offset) ix := ix -offset indexed addressing with index pre-decrement by the offset table 3-5. extended address mode description eleven different jump conditions are implemented as shown in table 3-6. the contents of the column cc in this table should replace the cc notation in the instructi on description of table 3-4. cc condition cs c=1 cc c=0 zs z=1 zc z=0 vs v=1 vc v=0 ev (ev1 or ev0)=1 after cmp op1,op2 eq op1=op2 ne op1 op2 gt op1>op2 ge op1 op2 lt op1 4-1 lc01 - 1.0 ? 10 october 2002 d0304-60 datasheet xe88lc01/01a 4 memory mapping 4.1 memory organisation 4-2 4.2 quick reference data memory register map 4-2 4.2.1 low power data registers (h0000-h0007) 4-3 4.2.2 system, clock configuration and re set configuration (h0010-h001f) 4-4 4.2.3 port a (h0020-h0027) 4-4 4.2.4 port b (h0028-h002f) 4-4 4.2.5 port c (h0030-h0033) 4-5 4.2.6 flash programming (h0038-003b) 4-5 4.2.7 event handler (h003c-h003f) 4-5 4.2.8 interrupt handler (h0040-h0047) 4-6 4.2.9 usrt (h0048-h004f) 4-7 4.2.10 uart (h0050-h0057) 4-7 4.2.11 counter/timer/pwm registers (h0058-h005f) 4-7 4.2.12 acquisition chain registers (h0060-h0067) 4-8 4.2.13 voltage multiplier (h007c) 4-8 4.2.14 voltage level detector registers (h007e-h007f) 4-8 4.2.15 ram (h0080-h027f) 4-8
4-2 d0304-60 datasheet xe88lc01/01a 4.1 memory organisation the xe88lc01 cpu is built with a harvard archit ecture. harvard architecture uses separate instruction and data memories. the instruction bus and data bus are also separated. the advantage of such a structure is that t he cpu can get a new instruction and read/write data simultaneously. the circuit configuration is shown in figure 4-1. the cpu has its 16 internal r egisters. the instruction memory has a capacity of 8192 22-bit instruct ions. the data memory space has 8 low power registers, the peripheral regist er space and 512 bytes of ram. figure 4-1. memory mapping the cpu internal registers are described in the cpu chapter. a short reference of the low power registers and peripheral regist ers is given in 4.2. 4.2 quick reference data memory register map the data register map is given in the tables bel ow. a more detailed description of the different registers is given in the detailed de scription of the different peripherals. the tables give the following information: 1. the register name and register address 2. the different bits in the register 3. the access mode of the different bits (see table 4-4-1 for code description) 4. the reset source and reset value of the different bits f
4-3 d0304-60 datasheet xe88lc01/01a the reset source coding is given in table 4-4-2. to get a full description of the reset sources, please refer to the reset block chapter. code access mode r bit can be read w bit can be written r0 bit always reads 0 r1 bit always reads 1 c bit is cleared by writing any value c1 bit is cleared by writing a 1 ca bit is cleared after reading s special function, verify the detailed description in the respective peripherals table 4-4-1. access mode codes us ed in the register definitions code reset source sys resetsystem cold resetcold pconf resetpconf sleep resetsleep table 4-4-2. reset source coding used in the register definitions 4.2.1 low power data registers (h0000-h0007) name address 7 6 5 4 3 2 1 0 reg00 h0000 reg00[7:0] rw, xxxxxxxx,- reg01 h0001 reg01[7:0] rw,xxxxxxxx,- reg02 h0002 reg02[7:0] rw,xxxxxxxx,- reg03 h0003 reg03[7:0] rw,xxxxxxxx,- reg04 h0004 reg04[7:0] rw,xxxxxxxx,- reg05 h0005 reg05[7:0] rw,xxxxxxxx,- reg06 h0006 reg06[7:0] rw,xxxxxxxx,- reg07 h0007 reg07[/:0] rw,xxxxxxxx,- table 4-4-3. low power data registers
4-4 d0304-60 datasheet xe88lc01/01a 4.2.2 system, clock configuration and reset configuration (h0010-h001f) name address 7 6 5 4 3 2 1 0 regsysctrl h0010 sleepen rw,0,cold enrespconf rw,0,cold enbuserror rw,0,cold enreswd rw,0,cold r0 r0 r0 r0 regsysreset h0011 sleep rw,0,sys resetbuserror rc, 0, cold resetwd rc, 0, cold resetfromporta rc, 0, cold respad rc,0,cold respadsleep rc,0,cold r0 regsysclock h0012 cpusel rw,0,sleep extclk r,0,cold enextclock rw,0,cold biasrc rw,1,cold coldxtal r,1,sleep coldrc r,1,sleep enablextal rw,0,sleep enablerc rw,1,sleep regsysmisc h0013 r0 r0 r0 r0 rconpa0 rw,0,sleep debfast rw,0,sleep outputckxta l rw,0,sleep outputcpuck rw,0,sleep regsyswd h0014 r0 r0 r0 r0 watchdog[3:0] s,0000,cold regsyspre0 h0015 r0 r0 r0 r0 r0 r0 r0 respre c1r0,0,- regsysrctrim1 h001b r0 r0 reserved rw,0,cold rcfreqrange rw,0,cold rcfreqcoarse[3:0] rw,0000,cold regsysrctrim2 h001c r0 r0 rcfreqfine[5:0] rw,10000,cold table 4-4-4. reset block and clock block registers 4.2.3 port a (h0020-h0027) name address 7 6 5 4 3 2 1 0 regpain h0020 pain[7:0] r regpadebounce h0021 padebounce[7:0] rw,00000000,pconf regpaedge h0022 paedge[7:0] rw,00000000,sys regpapullup h0023 papullup[7:0] rw,00000000,pconf regpares0 h0024 pares0[7:0] rw, 00000000, sys regpares1 h0025 pares1[7:0] rw,00000000,sys table 4-4-5. port a registers 4.2.4 port b (h0028-h002f) name address 7 6 5 4 3 2 1 0 regpbout h0028 pbout[7:0] rw,00000000,pconf regpbin h0029 pbin[7:0] r regpbdir h002a pbdir[7:0] rw,00000000,pconf regpbopen h002b pbopen[7:0] rw,00000000,pconf regpbpullup h002c pbpullup[7:0] rw,00000000,pconf regpbana h002d r0 r0 r0 r0 pbana[3:0] rw,0000,pconf table 4-4-6. port b registers
4-5 d0304-60 datasheet xe88lc01/01a 4.2.5 port c (h0030-h0033) name address 7 6 5 4 3 2 1 0 regpcout h0030 pcout[7:0] rw,00000000,pconf regpcin h0031 pcin[7:0] r,-,- regpcdir h0032 pd1dir[7:0] rw,00000000,pconf table 4-4-7. port c registers 4.2.6 flash programming (h0038-003b) these four registers are used during flash pr ogramming only. refer to the flash programming algorithm documentation for more details. 4.2.7 event handler (h003c-h003f) name address 7 6 5 4 3 2 1 0 regevn h003c cntirqa rc1,0,sys cntirqc rc1,0,sys 128hz rc1,0,sys paevn[1] rc1,0,sys cntirqb rc1,0,sys cntirqd rc1,0,sys 1hz rc1,0,sys paevn[0] rc1,0,sys regevnen h003d evnen[7:0] rw,00000000,sys regevnpriority h003e evnpriority[7:0] r,11111111,sys regevnevn h003f r0 r0 r0 r0 r0 r0 evnhigh r,0,sys evnlow r,0,sys table 4-4-8. event handler registers the origin of the different events is summarised in the table below. event event source cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) paevn[1:0] port a table 4-4-9. event source description
4-6 d0304-60 datasheet xe88lc01/01a 4.2.8 interrupt handler (h0040-h0047) name address 7 6 5 4 3 2 1 0 regirqhig h0040 irqac rc1,0,sys 128hz rc1,0,sys r0 cntirqa rc1,0,sys cntirqc rc1,0,sys r0 uartirqtx rc1,0,sys uartirqrx rc1,0,sys regirqmid h0041 usrtcond1 rc1,0,sys urstcond2 rc1,0,sys pairq[5] rc1,0,sys pairq[4] rc1,0,sys 1hz rc1,0,sys vldirq rc1,0,sys pairq[1] rc1,0,sys pairq[0] rc1,0,sys regirqlow h0042 pairq[7] rc1,0,sys pairq[6] rc1,0,sys cntirqb rc1,0,sys cntirqd rc1,0,sys pairq[3] rc1,0,sys pairq[2] rc1,0,sys r0 r0 regirqenhig h0043 irqenhig[7:0] rw,0000000,sys regirqenmid h0044 irqenmid[7:0] rw,0000000,sys regirqenlow h0045 irqenlow[7:0] rw,0000000,sys regirqpriority h0046 irqpriority[7:0] r,11111111,sys regirqirq h0047 r0 r0 r0 r0 r0 irqhig r,0,sys irqmid r,0,sys irqlow r,0,sys table 4-4-10. interrupt handler registers the origin of the different interrupts is summarised in the table below. event event source cntirqa counter/timer a (counter block) cntirqb counter/timer b (counter block) cntirqc counter/timer c (counter block) cntirqd counter/timer d (counter block) 128hz low prescaler (clock block) 1hz low prescaler (clock block) pairq[7:0] port a uartirqrx uart reception uartirqtx uart transmission urstcond1 usrt condition 1 usrtcond2 usrt condition 2 vldirq voltage level detector irqac acquisition chain end of conversion interrupt table 4-4-11. interrupt source description
4-7 d0304-60 datasheet xe88lc01/01a 4.2.9 usrt (h0048-h004f) name address 7 6 5 4 3 2 1 0 regusrts1 h0048 r0 r0 r0 r0 r0 r0 r0 usrts1 s,1,sys regusrts0 h0049 r0 r0 r0 r0 r0 r0 r0 usrts0 s,1,sys regusrtcond1 h004a r0 r0 r0 r0 r0 r0 r0 usrtcond1 rc,0,sys regusrtcond2 h004b r0 r0 r0 r0 r0 r0 r0 usrtcond2 rc,0,sys regusrtctrl h004c r0 r0 r0 r0 usrtwaits0 r,0,sys usrtenwaitcond1 rw,0,sys usrtenwaits0 rw,0,sys usrtenable rw,0,sys regusrtbuffers1 h004d r0 r0 r0 r0 r0 r0 r0 usrtbuffers1 r,0,sys regusrtedges0 h004e r0 r0 r0 r0 r0 r0 r0 usrtedges0 r,0,sys table 4-4-12. usrt register description 4.2.10 uart (h0050-h0057) name address 7 6 5 4 3 2 1 0 reguartctrl h0050 uartecho rw,0,sys uartenrx1 rw,0,sys uartentx rw,0,sys uartxrx rw,0,sys uartxtx rw,0,sys uartbr[2:0] rw,101,sys reguartcmd h0051 selxtal rw,0,sys uartenrx2 rw,0,sys uartrcsel[2:0] rw,000,sys uartpm rw,0,sys uartpe rw,0,sys uartwl rw,1,sys reguarttx h0052 uarttx[7:0] rw,0000000,sys reguarttxsta h0053 r0 r0 r0 r0 r0 r0 uarttxbusy r,0,sys uarttxfull r,0,sys reguartrx h0054 uartrx[7:0] r,00000000,sys reguartrxsta h0055 r0 r0 uartrxserr r,0,sys uartrxperr r,0,sys uartrxferr r,0,sys uartrxoerr rc,0,sys uartrxbusy r,0,sys uartrxfull r,0,sys table 4-13. uart register description 4.2.11 counter/timer/pwm registers (h0058-h005f) name address 7 6 5 4 3 2 1 0 regcnta h0058 countera[7:0] s,xxxxxxxx,- regcntb h0059 counterb[7:0] s,xxxxxxxx,- regcntc h005a counterc[7:0] s,xxxxxxxx,- regcntd h005b counterd[7:0] s,xxxxxxxx,- regcntctrlck h005c cntdcksel[1:0] rw,xx,- cntccksel[1:0] rw,xx,- cntbcksel[1:0] rw,xx,- cntacksel[1:0] rw,xx,- regcntconfig1 h005d cntddownup rw,x,- cntcdownup rw,x,- cntbdownup rw,x,- cntadownup rw,x,- cascadecd rw,x,- cascadeab rw,x,- cntpwm1 rw,0,sys cntpwm0 rw,0,sys regcntconfig2 h005e capsel[1:0] rw,00,sys capfunc[1:0] rw,00,sys pwm1size[1:0] rw,xx,- pwm0size[1:0] rw,xx,- regcnton h005f r0 r0 r0 r0 cntdenable rw,0,sys cntcenable rw,0,sys cntbenable rw,0,sys cntaenable rw,0,sys table 4-14. counter/timer/pwm register description.
4-8 d0304-60 datasheet xe88lc01/01a 4.2.12 acquisition chain registers (h0060-h0067) name address 7 6 5 4 3 2 1 0 regacoutlsb h0060 out[7:0] r,0,sys regacoutmsb h0061 out[15:8] r,0,sys regaccfg0 h0062 start w r0,0,sys set_nelconv[1:0] rw,01,sys set_osr[2:0] rw,010,sys cont rw,0,sys r0 regaccfg1 h0063 ib_amp_adc[1:0] rw,11,sys ib_amp_pga[1:0] rw,11,sys enable[3:0] rw,0000,sys regaccfg2 h0064 fin rw,00,sys pga2_gain[1:0] rw,00,sys pga2_offset[3:0] rw,0000,sys regaccfg3 h0065 pga1_gain rw,0,sys pga3_gain[6:0] rw,0000000,sys regaccfg4 h0066 r0 pga3_offset rw,0000000,sys regaccfg5 h0067 busy r,0,sys def w r0 amux[4:0] rw,00000,sys vmux rw,0,sys table 4-15. acquisition chain register description. 4.2.13 voltage multiplier (h007c) name address 7 6 5 4 3 2 1 0 regvmultcfg0 h007c r0 r0 r0 r0 r0 enable rw,0,sys fin[1:0] rw,00,sys table 4-16. vmult register. 4.2.14 voltage level detector registers (h007e-h007f) name address 7 6 5 4 3 2 1 0 regvldctrl h007e r0 r0 r0 r0 vldrange rw,0,sys vldtune[2:0] rw,000,sys regvldstat h007f r0 r0 r0 r0 r0 vldresult r,0,sys vldvalid r,0,sys vlden rw,0,sys table 4-17. voltage level detector register description 4.2.15 ram (h0080-h027f) the 512 ram bytes can be accessed for read and writ e operations. the ram has no reset function. variables stored in the ram should be initialised befor e use since they can have any value at circuit start up.
5-1 system_ff - 1.0 ? 27 september 2002 d0304-60 datasheet xe88lc01/01a 5 system block 5.1 overview 5-2 5.2 operating mode 5-2
5-2 d0304-60 datasheet xe88lc01/01a 5.1 overview the xe8000 chips have three operating modes. there ar e; normal, low current and very low current modes (see figure 5-1). the different modes are controlled by the reset and clock blocks (see the documentation of the respective blocks). 5.2 operating mode start-up all bits are reset in the design when a por (power-on-reset) is active. rc is enabled, xtal is disabled and the cpu is reset (pmaddr = 0000). if the port a is used to return from the sleep m ode, all bits with resetcold don?t change (see sleep mode) reset all bits with resetsystem and resetpconf (if enabled) are reset. clock configuration doesn?t change except cpuck. the cpu is reset active mode this is the mode where the cpu and all peripher als can work and execute the embedded software. standby mode executing a halt instruction moves the xe8000 into the standby mode. the cp u is stopped, but the clocks remain active. therefor, the enabled peripherals re main active e.g. for time keeping. a reset or an interrupt/event request (if enabled) cancels the standby mode. sleep mode this is a very low-power mode because all circui t clocks and all peripherals are stopped. only some service blocks remain active. no time-keeping is po ssible. two instructions are necessary to move into sleep mode. first, the sleepen (sleep enable) bit in regsysctrl has to be set to 1. the sleep mode can then be activated by setting the sleep bit in regsysreset to 1. there are three possibe ways to wake-up from the sleep mode: 1. the por (power-on-reset caused by a power-down followed by power-on). the ram information is lost. 2. the padreset 3. the port a reset combination (if the port a is present in the product). see port a documentation for more details. note : if the port a is used to return from the sleep mode, all bits with resetcold don?t change ( regsysctrl , regsysreset (except bit sleep ), enextclock and biasrc in regsysclock , regsysrctrim1 and regsysrctrim2 ). the sleepflag bit in regsysreset , reads back a 1 if the circuit was in sleep mode since the fl ag was last cleared (see reset block for more details). note : for a lower power consumption, disable the biasrc bit in regsysclock before to going to sleep mode. the start-up time of the oscillator will then be longer however. note : it is recommended to insert a nop instruction afte r the instruction that se ts the circuit in sleep mode because this instruction can be exec uted when the sleep mode is left using the resetfromporta.
5-3 d0304-60 datasheet xe88lc01/01a start-up reset active stand-by sleep halt instruction interrupt/event set bit sleep po r padreset porta reset po r normal mode low current very low current po r padreset porta reset watchdog reset buserror reset padreset porta reset watchdog reset por without condition without condition figure 5-1. xe88lc01 operating modes.
6-1 reset_ff - 1.1 ? 16 april 2003 d0304-60 datasheet xe88lc01/01a 6 reset block 6.1 features 6-2 6.2 overview 6-2 6.3 register map 6-2 6.4 reset handling capabilities 6-3 6.5 reset source description 6-4 6.5.1 power on reset 6-4 6.5.2 reset pin 6-4 6.5.3 programmable port a input combination 6-4 6.5.4 watchdog reset 6-4 6.5.5 buserror reset 6-4 6.5.6 sleep mode 6-4 6.6 control register description and operation 6-4 6.7 watchdog 6-5 6.8 start-up and watchdog specifications 6-5
6-2 d0304-60 datasheet xe88lc01/01a 6.1 features ? power on reset (por) ? external reset from the reset pin ? programmable watchdog timer reset ? programmable buserror reset ? sleep mode management ? programmable port a input combination reset 6.2 overview the reset block is the reset manager. it handles t he different reset sources and distributes them through the system. it also controls the sleep mode of the circuit. 6.3 register map pos. regsysctrl rw reset function 7 sleepen r w 0 resetcold enables sleep mode 0: sleep mode is disabled 1: sleep mode is enabled 6 enrespconf r w 0 resetcold enables the resetpconf signal when the resetglobal is active 0: resetpconf is disabled 1: resetpconf is enabled 5 enbuserror r w 0 resetcold enables reset from buserror 0: buserror reset source is disabled 1: buserror reset source is enabled 4 enreswd r w 0 resetcold enables reset from watchdog 0: watchdog reset source is disabled 1: watchdog reset source is enabled this bit can not be set to 0 by sw 3 ? 0 - r 0000 unused table 6-1. regsysctrl register. pos. regsysreset rw reset function 7 sleep rw 0 resetsystem sleep mode control (reads always 0) 6 - r 0 unused 5 resetbuserror r c 0 resetcol d reset source was buserror 4 resetwd r c 0 resetcold reset source was watchdog 3 resetfromporta r c 0 resetcold rese t source was port a combination 2 respad r c 0 resetcold reset source was reset pad 1 respadsleep r c 0 resetcold reset source was reset pad in sleep mode 0 - r 0 unused table 6-2. regsysreset register
6-3 d0304-60 datasheet xe88lc01/01a pos. regsyswd rw reset function 7 ? 4 - r 0000 unused wdkey[3] w watchdog key bit 3 3 wdcounter[3] r 0 resetcold watchdog counter bit 3 wdkey[2] w watchdog key bit 2 2 wdcounter[2] r 0 resetcold watchdog counter bit 2 wdkey[1] w watchdog key bit 1 1 wdcounter[1] r 0 resetcold watchdog counter bit 1 wdkey[0] w watchdog key bit 0 0 wdcounter[0] r 0 resetcold watchdog counter bit 0 table 6-3. regsyswd register 6.4 reset handling capabilities there are 5 reset sources: ? power on reset (por) ? external reset from the reset pin ? programmable port a input combination ? programmable watchdog timer reset ? programmable buserror reset on processor access outside the allocated memory map another reset source is the bit sleep in the regsysreset register. this source is fully controlled by software and is only used during the sleep mode. four internal reset signals are generated from these sources and distri buted through the system: ? resetcold: is asserted on por ? resetsystem: is asserted when resetcold or any other enabled reset source is active ? resetpconf: is asserted when rese tsystem is active and if the enrespconf bit in the regsysctrl register is set. this reset is gener ally used in the different ports. it allows to maintain the port configuration unchanged while the rest of the circuit is reset. ? resetsleep: is asserted when the circuit is in sleep mode for the circuits XE88LC01A and xe88lc05a (2) for the circuits xe88lc01 and xe88lc05 table 6-4 shows a summary of the dependency of t he internal reset signals on the various reset sources. in all the tables describing the different registers, the reset source is indicated. internal reset signals resetpconf asserted reset source resetsystem when enrespconf=0 when enrespconf=1 resetsleep resetcold por asserted asserted asserted asserted asserted reset pin (1) asserted assert ed asserted asserted asserted reset pin (2) asserted - asserted - - porta input asserted - asserted - - watchdog asserted - asserted - - buserror asserted - asserted - - sleep - - - asserted - (1) for the circuits XE88LC01A and xe88lc05a (2) for the circuits xe88lc01 and xe88lc05 table 6-4 internal reset assertion as a function of the reset source.
6-4 d0304-60 datasheet xe88lc01/01a 6.5 reset source description 6.5.1 power on reset the power on reset (por) monitors the external supply voltage. it activates a reset on a rising edge of this supply voltage. the reset is inactivated only if the internal voltage regulator has started up. no precise voltage level detection is performed by the por block. 6.5.2 reset pin the reset can be activated by applying a high input state on the reset pin. 6.5.3 programmable port a input combination a reset signal can be generated by port a. see the descr iption of the port a for further information. 6.5.4 watchdog reset the watchdog will generate a reset if the enresetwd bit in the regsysctrl register has been set and if the watchdog is not cleared in time by the proc essor. see chapter 6.7 describing the watchdog for further information. 6.5.5 buserror reset the address space is assigned as shown in the register map of the product. if the enbuserror bit in the regsysctrl register is set and a non-existant address is accessed by the software, a reset is generated. 6.5.6 sleep mode entering the sleep mode will reset a part of the circui t. the reset is used to configure the circuit for correct wake-up after the sleep mode. if the sleepen bit in the regsysctrl register has been set, the sleep mode can be entered by setting the bit sleep in regsysreset . during the sleep mode, the resetsleep signal is active. for detailed in formation on the sleep m ode, see the system documentation. 6.6 control register description and operation two registers are dedicated fo r reset status and control, regsysreset and regsysctrl . the bits sleep , and sleepen are also located in those registers and are described in the chapter dedicated to the different operating modes of the circuit (system block). the regsysreset register gives information on the source which generated the last reset. it can be read at the beginning of the application program to detec t if the circuit is recovering from an error or exception condition, or if the circuit is starting up normally. ? when resbuserror is 1, a forbidden address access generated the reset. ? when reswd is 1, the watchdog generated the reset. ? when resporta is 1, a porta combination generated the reset. ? when respad is 1, a reset pin generated the reset. ? when respadsleep is 1, a reset pin in sleep mode generated the reset. note: if no bit is set to 1, the reset source was the internal por. note: several bits might be set or not, if the register was not cleared in between 2 reset occurrences. write any value in regsysreset to clear it. note: when a reset pin wakes up the chip from the sleep mode, respad and respadsleep bits are equal at 1.
6-5 d0304-60 datasheet xe88lc01/01a the last bit concerns the sleep mode contro l (see system documentation for the sleep mode description). ? when sleep is set to 1, and sleepen is 1, the sleep mode is entered. the bit always reads back a 0. the regsysctrl register enables the different available reset sources and the sleep mode. ? enreswd enables the reset due to the watchdog (can not be disabled once enabled). ? enbuserror enables the reset due to a bus error condition. ? enrespconf enables the reset of the port configurati ons when reset by port a, a bus error or the watchdog. ? sleepen unlocks the sleep bit. as long as sleepen is 0, the sleep bit has no effect. 6.7 watchdog the watchdog is a timer which has to be cleared at l east every 2 seconds by th e software to prevent a reset being generated by the timeout condition. the watchdog can be enabled by software by setting the enreswd bit in the regsysctrl register to 1. it can then only be disabled by a power on reset. the watchdog timer can be cleared by writing consecutively the values hx0a and hx03 to the regsyswd register. the sequence must strictly be respected to clear the watchdog. in assembler code, the sequence to clear the watchdog is: move addrregsyswd, #0x0a move addrregsyswd, #0x03 only writing hx0a followed by hx 03 resets the wd. if some other write instruction is done to the regsyswd between the writing of the hx0a and hx03 va lues, the watchdog timer will not be cleared. it is possible to read the status of the watchdog in the regsysw d register. the watchdog is a 4 bit counter with a count range between 0 and 7. the system reset is generated when the counter is reaching the value 8. 6.8 start-up and watchdog specifications at start-up of the circuit, the por (power-on -reset) block generates a reset signal during t por . the circuit starts software execution after this period (see system chapter). the por is intended to force the circuit in a correct state at start-up. for precise monitoring of the supply voltage, the voltage level detector (vld) has to be used.
6-6 d0304-60 datasheet xe88lc01/01a symbol parameter min typ max unit comments t por por reset duration 5 20 ms t reset reset pin reset duration 20 200 s 3 t reset reset pin reset duration 5 20 ms 4 vbat_sl_m supply ramp up of mtp version 20 v/ms 1 vbat_sl_r supply ramp up of rom version 0.25 v/ms 1 wdtime watchdog timeout period 2 s 2 table 6-5. electrical and timing specifications note: 1) the vbat_sl defines the minimum slope requi red on vbat. correct start-up of the circuit is not guaranteed if this slope is too slow. in such a ca se, a delay has to be built using the reset pin. note: 2) the minimal watchdog timeout period is guar anteed when the internal oscillators are used. the watchdog takes its clock from the low prescaler. in case an external clock source is used, the rc oscillator must be enabled also ( enrc =1 in regsysclock ). otherwise, the watchdog is stopped (see the clock block documentation). note: 3) for the circuit versions xe88lc01 and xe88lc05. gives the time the reset is active after the falling edge of the reset pin. note: 4) for the circuit versions XE88LC01A and xe88lc05a . gives the time the reset is active after the falling edge of the reset pin.
7-1 clock_gen_ff - 1.0 ? 19 august 2002 d0304-60 datasheet xe88lc01/01a 7 clock generator 7.1 features 7-2 7.2 overview 7-2 7.3 register map 7-2 7.4 interrupts and events map 7-4 7.5 clock sources 7-4 7.5.1 rc oscillator 7-4 7.5.2 xtal oscillator 7-6 7.5.3 external clock 7-7 7.6 clock source selection 7-8 7.7 regsysmisc description 7-8 7.8 prescalers 7-9 7.9 32 khz frequency selector 7-9
7-2 d0304-60 datasheet xe88lc01/01a 7.1 features ? 3 available clock sources (rc oscillator, quartz oscillator and external clock). ? 2 divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). ? cpu clock disabling in halt mode. 7.2 overview the xe88lc01 chips can work on different clock sour ces (rc oscillator, quartz oscillator and external clock). the clock generator block is in charge of distributing the necessary clock frequencies to the circuit. figure 7-1 represents the functi onality of the clock block. the internal rc oscillator drives the high presca ler. this prescaler generates frequency divisions down to 1/256 of its input frequency. a 32khz clo ck is generated by enabling the quartz oscillator (if present in the product) or by selecting the appropr iate tap on the high prescaler. the low prescaler generates clock signals from 32khz down to 1hz. t he clock source for the cpu can be selected from the rc oscillator, the external clock or the 32khz clock. 7.3 register map pos. regsysclock rw reset function 7 cpusel rw 0 resetsleep select speed for cpuck, 0=rc, 1=xtal or external clock 6 extclk r 0 resetcold external clock detected, 1=available 5 enextclock rw 0 resetcold enable for external clock, 1=enabled 4 biasrc rw 1 resetcold enable rcbi as (reduces start-up time of rc). 3 coldxtal r 1 resetsleep xtal in start phase 2 coldrc r 1 resetsleep rc in start phase 1 enablextal rw 0 resetsleep enable xt al oscillator, 0=disabled, 1=enabled 0 enablerc rw 1 resetsleep enable rc oscillator, 0=disabled, 1=enabled table 7-1: regsysclock register pos. regsysmisc rw reset function 7-4 -- r 0000 unused 3 rconpa0 rw 0 resetsleep start rc on pa[0], 0=disabled, 1=enabled 2 debfast rw 0 resetsleep debouncer clock speed, 0=256hz, 1=8khz 1 outputckxtal rw 0 resetsleep out put xtal clock on pb[3], 0=disabled, 1=enabled if enxtal =1 else pb[3]=0 0 outputcpuck rw 0 resetsleep out put cpu clock on pb[2], 0=disabled, 1=enabled table 7-2: regsysmisc register pos. regsyspre0 rw reset function 7-1 -- r 0000000 unused 0 respre w1 r0 0 write 1 to reset low prescaler, but always reads 0 table 7-3 : regsyspre0 register
7-3 d0304-60 datasheet xe88lc01/01a pos. regsysrctrim1 rw reset function 7-4 -- r 00 unused 5 reserved rw 0 resetcold reserved 4 rcfreqrange rw 0 resetcold low/high freq. range (low=0) 3 rcfreqcoarse[3] rw 0 resetcold rc coarse trim bit 3 2 rcfreqcoarse[2] rw 0 resetcold rc coarse trim bit 2 1 rcfreqcoarse[1] rw 0 resetcold rc coarse trim bit 1 0 rcfreqcoarse[0] rw 0 resetcold rc coarse trim bit 0 table 7-4: regsysrctrim1 register pos. regsysrctrim2 rw reset function 7-6 -- r 00 unused 5 rcfreqfine[5] rw 1 resetcold rc fine trim bit 5 4 rcfreqfine[4] rw 0 resetcold rc fine trim bit 4 3 rcfreqfine[3] rw 0 resetcold rc fine trim bit 3 2 rcfreqfine[2] rw 0 resetcold rc fine trim bit 2 1 rcfreqfine[1] rw 0 resetcold rc fine trim bit 1 0 rcfreqfine[0] rw 0 resetcold rc fine trim bit 0 table 7-5: regsysrctrim2 register oscin rc xtal high prescaler cpuck cpusel 0 1 regsysrctrim1 regsysrctrim2 0 1 ckrc ckxtal enxtal and not( extclk or enextclk ) low prescaler 32khz to 1hz ckrc to ckrc/256 external clock 0 1 figure 7-1. clock block structure
7-4 d0304-60 datasheet xe88lc01/01a 7.4 interrupts and events map interrupt interrupt source mapping in the interrupt manager mapping in the event manager irqpre1 ck128hz regirqhig(6) regevn(5) irqpre2 ck1hz regirqmid(3) regevn(1) table 7-6: interrupts and events map 7.5 clock sources 7.5.1 rc oscillator 7.5.1.1 configuration the rc oscillator is always turned on and selected for cpu and system operation at power-on reset and when exiting sleep mode. it can be turned off afte r the xtal (quartz oscillator) has been started, after selection of the external clock or by entering sleep mode. the rc oscillator has two frequency ranges: sub-mhz (100 khz to 1 mhz) and above-mhz (1 mhz to 10 mhz). inside a range, the frequency can be tuned by software for coarse and fine adjustment. see registers regsysrctrim1 and regsysrctrim2 . bit enablerc in register regsysclock controls the propagation of the rc clock signal and the operation of the oscillator. the user can stop the rc oscillator by resetting the bit enablerc . entering the sleep mode disables the rc oscillator. note : before turning off the rc oscillator, the cpusel bit in regsysclock must be set to one. note : the rc oscillator bias can be maintained while t he oscillator is switched off by setting the bit biasrc in regsysclock . this allows a faster restart of t he rc oscillator at the cost of increased power consumption when the oscillator is disabled (see section 7.5.1.3). 7.5.1.2 rc oscillator frequency tuning the rc oscillator frequency can be set using the bits in the regsysrctrim1 and regsysrctrim2 registers. figure 7-2 shows the nominal frequency of the rc oscillator as a function of these bits. the absolute value of the frequency for a gi ven register content may change by 50% from chip to chip due to the tolerances on the integrated capacitors and resistors. however, the modification of the frequency as a function of a modification of the regist er content is fairly precise for frequencies below 2mhz. this means that the curves in figure 7- 2 can shift up and down but that the slope remains unchanged. the bit rcfreqrange modifies the oscillator frequency by a fa ctor of 10. the upper curve in the figure corresponds to rcfreqrange =1. the rcfreqcoarse modifies the frequency of the oscillator by a factor ( rcfreqcoarse +1). the figure represents the frequency for 5 different values of the bits rcfreqcoarse : for each value the frequency is multiplied by 2. incrementing the rcfreqfine code increases the frequency by about 1.4%. the frequency of the oscillator is therefor given by:
7-5 d0304-60 datasheet xe88lc01/01a f rc =f rcmin ? (1+9 ? rcfreqrange ) ? (1+ rcfreqcoarse ) ? (1.014) rcfreqfine with f rcmin the rc oscillator frequency if the registers are all 0. at higher frequencies, the frequency may deviate from the value predicted by the equation. 00 0 0 0 0 010000 10 0 0 0 0 1 1 0 0 0 0 11 1 1 1 1 0100 0 0 1 0 0 00 0 110000 1111 1 1 0 1 00 0 0 100000 110000 1 1 1 1 11 0 10000 10000 0 1 1 0 0 00 11 1 1 1 1 010 0 00 1 0 00 0 0 1 1 0000 111111 00 0 000 01 0 0 0 0 1 00000 11000 0 11 1 111 0 1 0 000 100000 1 1 00 0 0 1 1 1 1 1 1 010 0 00 10 0 0 0 0 1 1 0 0 0 0 111111 0 1 0 0 0 0 1 0 0 0 00 1100 0 0 111111 0 1 00 0 0 10 0 000 1 1 00 0 0 1 1 1 1 1 1 0000 0001 0011 0111 1111 1e+04 1e+05 1e+06 1e+07 1e+08 rcfreqcoarse(3:0) nominal rc oscillator frequency [hz] rcfreqrange='1' rcfreqrange='0' rcfreqfine(5:0) rcfreqfine(5:0) figure 7-2. rc oscillator nominal frequency tuning. 7.5.1.3 rc oscillator specifications symbol description min typ max unit comments f rcmin lowest rc frequency 40 80 120 khz note 1 rcfreqfine fine tuning step 1.4 2.0 % rc_su startup time 30 50 us biasrc =0 3 5 us biasrc =1 psrr @ dc supply voltage tbd %/v note 2 dependence tbd %/v note 3 ? f/ ? t temperature dependence 0.1 %/ c table 7-7. rc oscillator specifications note 1: this is the frequency tolerance when all trimming codes are 0. note 2: frequency shift as a function of vbat with normal regulator function. note 3: frequency shift as a function of vbat while t he regulator is short-circuited to vbat.
7-6 d0304-60 datasheet xe88lc01/01a the tolerances on the minimal frequency and the dri ft with supply or temperature can be cancelled using the software dfll (digital frequency locked l oop) which uses the crystal oscillator as a reference frequency. 7.5.2 xtal oscillator 7.5.2.1 xtal configuration the xtal operates with an external crystal of 32?768 hz. during xtal oscillator start-up, the firs t 32768 cycles are masked. the two bits enablextal and coldxtal in register regsysclock control the oscillator. at power-on reset or during sleep mode, enablextal is reset and coldxtal is set (xtal oscillator is not selected at start-up). the user c an start xtal oscillator by setting enablextal . when the xtal oscillator starts, bit coldxtal is reset after 32768 cycles. before coldxtal is reset by the system, the xtal frequency precision is not guaranteed. the xtal osc illator can be stopped by the user by resetting bit enablextal . when the user enters into sleep mode, the xtal is stopped. when an external clock is detected ( extclk = 1) or the enextclock is set 1, the enablextal bit can not be set to 1. 7.5.2.2 xtal oscillator specifications the crystal oscillator has been designed for a crystal wi th the specifications given in table 7-8. the oscillator precision can only be guaranteed for this crystal. symbol description min typ max unit comments fs resonance frequency 32768 hz cl cl for nominal frequency 8.2 15 pf rm motional resistance 40 100 k ? cm motional capacitance 1.8 2.5 3.2 ff c0 shunt capacitance 0.7 1.1 2.0 pf rmp motional resistance of 6 th overtone (parasitic) 4 8 k ? q quality factor 30k 50k 400k - table 7-8. crystal specifications. for safe operation, low power consumption and to m eet the specified precision, careful board layout is required: keep lines oscin and oscout short and insert a vss line in between them. connect the crystal package to vss. no noisy or digital lines near oscin or oscout. insert guards where needed. respect the board specifications of table 7-9.
7-7 d0304-60 datasheet xe88lc01/01a symbol description min typ max unit comments rh_oscin resistance oscin-vss 10 m ? rh_oscout resistance oscout-vss 10 m ? rh_ oscin_oscout resistance oscin-oscout 50 m ? cp_oscin capacitance oscin-vss 0.5 3.0 pf cp_oscout capacitance oscout-vss 0.5 3.0 pf cp_ oscin_oscout capacitance os cin-oscout 0.2 1.0 pf table 7-9. board layout specifications. the oscillator characteristics are given in table 7-10. the characteristics are valid only if the crystal and board layout meet the specifications above. symbol description min typ max unit comments f xtal nominal frequency 32768 hz st_xtal start-up time 1 2 s fstab frequency deviation -100 300 ppm note 1 table 7-10. crystal oscillator characteristics. note 1. this gives the relative frequency deviati on from nominal for a crystal with cl=8.2pf and within the temperature range -40 c to 85 c. the crystal tolerance, crystal aging and crystal temperature drift are not included in this figure. 7.5.3 external clock 7.5.3.1 external clock configuration the user can provide an external clock instead of t he internal oscillators. only the cpu can use the external clock. the external clock input pin is oscin. the system is configured for external clock by bit enextclock in register regsysclock . when enextclock is set to 1, the external clock is detected after 4 pulses on pin oscin. the extclk bit shows when the external clock is available. note: when using the external clock, the xtal is not available. 7.5.3.2 external clock specification the external clock has to satisfy the specifications in the table below. corre ct behavior of the circuit can not be guaranteed if the external clock signal does not respect the specifications below. symbol description min typ max unit comments f ext external clock frequency 2 mhz pw_1 pulse 1 width 0.2 s pw_0 pulse 0 width 0.2 s table 7-11. external clock specifications.
7-8 d0304-60 datasheet xe88lc01/01a 7.6 clock source selection there are three possible clock sources available fo r the cpu clock. the rc clock is always selected after power-up or after sleep mode. the cpu clock selection is done with the bit cpusel in regsysclock (0= rc clock, 1= 32 khz from xtal if enablextal =1, extclk = 0 and enextclk = 0 else external clock). switching from one clock source to another is glitch free. the next table summarizes the different cl ock configurations of the circuit: clock sources clock targets cpuck note 1 mode name enextclk enablerc enablextal cpusel =0 cpusel =1 high prescaler clock input low prescaler clock input sleep 0 0 0 off off off off xtal 0 0 1 off xtal off xtal rc 0 1 0 rc rc rc high presc. rc + xtal 0 1 1 rc xtal rc xtal external 1 0 x off external off off rc + external 1 1 x rc external rc high presc. table 7-12: table of clocking modes. note 1: the cpu clock can be divided by using the fr eq instruction (see cool risc instruction set) switching from one clock source to another and stopping the unused clock source must be performed using 3 move instructions to regsysclock . first select the new clock source, secondly change the cpusel bit and finally stop the unused one. 7.7 regsysmisc description the rconpa0 bit in regsysmisc can be used to enable the rc oscillator on an event external to the circuit. if rconpa0 is 1, the rc oscillator is enabled ( enablerc bit is set to 1) as soon as the value on port a pin pa[0] is equal to 1. the po rt a pin can be debounced (see port a documentation). bit debfast in the regsysmisc register allows to chose the debouncer clock between 256hz and 8khz (debfast = 0 and debfast = 1 respective ly). the debouncer clock is used to debounce pa inputs (see port a documentation). bit outputckxtal allows to show the xtal clock on pb[3]. the enablextal bit must be set to 1 else pb[3] equals 0 (see port b documentation to set up the port b). bit outputcpuck allows to show the c puclock on pb[2] (see port b documentation).
7-9 d0304-60 datasheet xe88lc01/01a 7.8 prescalers the clock generator block embeds two divider chai ns: the high prescaler and the low prescaler. the high prescaler is made of an 8 stage dividing chain and the low prescaler of a 15 stage dividing chain. features: ? high prescaler can only be driven with rc clock (bit enablerc have to be set, see table 7-12). ? low prescaler can be driven from the high presca ler or directly with the xtal clock when bit enablextal is set to 1, bit enextclock is set to 0 and extclk is equal at 0. ? bit respre in the regsyspre0 register allows to reset synchr onously the low prescaler, the low prescaler is also automatically cleared when bit enablextal is set. both dividing chains are reset asynchronously by the resetsleep signal. ? bit coldxtal =1 indicates the xtal is in its start up phas e. it is active for 37268 xtal cycles after setting enablextal . 7.9 32 khz frequency selector a decoder is used to select from the high prescaler the frequency tap that is the closest to 32 khz to operate the low prescaler when the xtal is not r unning. in this case, the rc oscillator frequency of 50% will also be valid for the low prescaler frequency outputs.
8-1 irq_ff - 1.0 ? 28 august 2002 d0304-60 datasheet xe88lc01/01a 8 irq - interrupt handler 8.1 features 8-2 8.2 overview 8-2 8.3 register map 8-2
8-2 d0304-60 datasheet xe88lc01/01a 8.1 features the xe8000 chips support 24 interrupt sources, divided into 3 levels of priority. 8.2 overview a cpu interruption is generated and memorized when an interrupt becomes active. the 24 interrupt sources are divided into 3 levels of priority: high (8 interrupt sources), mid (8 interrupt sources), and low (8 interrupt sources). those 3 levels of pr iority are directly mapped to those supported by the coolrisc (in0, in1 and in2; see coolrisc documentation for more information). regirqhig , regirqmid , and regirqlow are 8-bit registers containing fl ags for the interrupt sources. those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers regirqenhig , regirqenmid or regirqenlow is set) and a rising edge is detected on the corresponding interrupt source. once memorized, an interrupt flag can be cleared by writing a ?1? in the corresponding bit of regirqhig , regirqmid or regirqlow . writing a ?0? does not modify the flag. to definitively clear the interrupt, one has to clear the coolrisc interrupt in the coolrisc status regi ster. all interrupts are automatically cleared after a reset. two registers are provided to facilitate t he writing of interrupt service software. regirqpriority contains the number of the highest priority interrupt set (its value is 0xff when no interrupt is set). regirqirq indicates the priority leve l of the current interrupts. regirqirq and regirqpriority ?s values are dependent upon the memorized state of the interrupts (as reflected in flags in regirqhig , regirqmid and regirqlow ). 8.3 register map pos. regirqhig rw reset function 7 regirqhig[7] r c1 0 resetsystem interrupt #23 (high priority) clear interrupt #23 when 1 is written 6 regirqhig[6] r c1 0 resetsystem interrupt #22 (high priority) clear interrupt #22 when 1 is written 5 regirqhig[5] r c1 0 resetsystem interrupt #21 (high priority) clear interrupt #21 when 1 is written 4 regirqhig[4] r c1 0 resetsystem interrupt #20 (high priority) clear interrupt #20 when 1 is written 3 regirqhig[3] r c1 0 resetsystem interrupt #19 (high priority) clear interrupt #19 when 1 is written 2 regirqhig[2] r c1 0 resetsystem interrupt #18 (high priority) clear interrupt #18 when 1 is written 1 regirqhig[1] r c1 0 resetsystem interrupt #17 (high priority) clear interrupt #17 when 1 is written 0 regirqhig[0] r c1 0 resetsystem interrupt #16 (high priority) clear interrupt #16 when 1 is written table 8-1: regirqhig
8-3 d0304-60 datasheet xe88lc01/01a pos. regirqmid rw reset function 7 regirqmid[7] r c1 0 resetsystem interrupt #15 (mid priority) clear interrupt #15 when 1 is written 6 regirqmid[6] r c1 0 resetsystem interrupt #14 (mid priority) clear interrupt #14 when 1 is written 5 regirqmid[5] r c1 0 resetsystem interrupt #13 (mid priority) clear interrupt #13 when 1 is written 4 regirqmid[4] r c1 0 resetsystem interrupt #12 (mid priority) clear interrupt #12 when 1 is written 3 regirqmid[3] r c1 0 resetsystem interrupt #11 (mid priority) clear interrupt #11 when 1 is written 2 regirqmid[2] r c1 0 resetsystem interrupt #10 (mid priority) clear interrupt #10 when 1 is written 1 regirqmid[1] r c1 0 resetsystem interrupt #9 (mid priority) clear interrupt #9 when 1 is written 0 regirqmid[0] r c1 0 resetsystem interrupt #8 (mid priority) clear interrupt #8 when 1 is written table 8-2: regirqmid pos. regirqlow rw reset function 7 regirqlow[7] r c1 0 resetsystem interrupt #7 (low priority) clear interrupt #7 when 1 is written 6 regirqlow[6] r c1 0 resetsystem interrupt #6 (low priority) clear interrupt #6 when 1 is written 5 regirqlow[5] r c1 0 resetsystem interrupt #5 (low priority) clear interrupt #5 when 1 is written 4 regirqlow[4] r c1 0 resetsystem interrupt #4 (low priority) clear interrupt #4 when 1 is written 3 regirqlow[3] r c1 0 resetsystem interrupt #3 (low priority) clear interrupt #3 when 1 is written 2 regirqlow[2] r c1 0 resetsystem interrupt #2 (low priority) clear interrupt #2 when 1 is written 1 regirqlow[1] r c1 0 resetsystem interrupt #1 (low priority) clear interrupt #1 when 1 is written 0 regirqlow[0] r c1 0 resetsystem interrupt #0 (low priority) clear interrupt #0 when 1 is written table 8-3: regirqlow pos. regirqenhig rw reset function 7 regirqenhig[7] rw 0 resetsystem 1= enable interrupt #23 6 regirqenhig[6] rw 0 resetsystem 1= enable interrupt #22 5 regirqenhig[5] rw 0 resetsystem 1= enable interrupt #21 4 regirqenhig[4] rw 0 resetsystem 1= enable interrupt #20 3 regirqenhig[3] rw 0 resetsystem 1= enable interrupt #19 2 regirqenhig[2] rw 0 resetsystem 1= enable interrupt #18 1 regirqenhig[1] rw 0 resetsystem 1= enable interrupt #17 0 regirqenhig[0] rw 0 resetsystem 1= enable interrupt #16 table 8-4: regirqenhig
8-4 d0304-60 datasheet xe88lc01/01a pos. regirqenmid rw reset function 7 regirqenmid[7] rw 0 resetsystem 1= enable interrupt #15 6 regirqenmid[6] rw 0 resetsystem 1= enable interrupt #14 5 regirqenmid[5] rw 0 resetsystem 1= enable interrupt #13 4 regirqenmid[4] rw 0 resetsystem 1= enable interrupt #12 3 regirqenmid[3] rw 0 resetsystem 1= enable interrupt #11 2 regirqenmid[2] rw 0 resetsystem 1= enable interrupt #10 1 regirqenmid[1] rw 0 resetsystem 1= enable interrupt #9 0 regirqenmid[0] rw 0 resetsystem 1= enable interrupt #8 table 8-5: regirqenmid pos. regirqenlow rw reset function 7 regirqenlow[7] rw 0 resetsystem 1= enable interrupt #7 6 regirqenlow[6] rw 0 resetsystem 1= enable interrupt #6 5 regirqenlow[5] rw 0 resetsystem 1= enable interrupt #5 4 regirqenlow[4] rw 0 resetsystem 1= enable interrupt #4 3 regirqenlow[3] rw 0 resetsystem 1= enable interrupt #3 2 regirqenlow[2] rw 0 resetsystem 1= enable interrupt #2 1 regirqenlow[1] rw 0 resetsystem 1= enable interrupt #1 0 regirqenlow[0] rw 0 resetsystem 1= enable interrupt #0 table 8-6: regirqenlow pos. regirqpriority rw reset function 7-0 regirqpriority r 11111111 resetsystem code of highest priority set table 8-7: regirqpriority pos. regirqirq rw reset function 7-3 - r 00000 unused 2 irqhig r 0 resetsystem one or more high priority interrupt is set 1 irqmid r 0 resetsystem one or more mid priority interrupt is set 0 irqlow r 0 resetsystem one or more low priority interrupt is set table 8-8: regirqirq
9-1 evn_ff - 1.0 ? 28 august 2002 d0304-60 datasheet xe88lc01/01a 9 event handler 9.1 features 9-2 9.2 overview 9-2 9.3 register map 9-2
9-2 d0304-60 datasheet xe88lc01/01a 9.1 features the xe88lc01 chips support 8 event sources, divided into 2 levels of priority. 9.2 overview a cpu event is generated and memorized when an ev ent source becomes active. the 8 event sources are divided into 2 levels of priority: high (4 event sources) and low (4 event sources). those 2 levels of priority are directly mapped to those supported by the coolrisc (ev0 and ev1; see coolrisc documentation for more information). regevn is an 8-bit register containing flags for the ev ent sources. those flags are set when the event is enabled (i.e. if the corresponding bit in the registers regevnen is set) and a rising edge is detected on the corresponding event source. once memorized, writing a ?1? in the corresponding bit of regevn clears an event flag. writing a ?0? does not modify the flag. all interrupts are automatically cleared after a reset. two registers are provided to facilitate the writing of event service software. regevnpriority contains the number of the highest priority event set (its value is 0xff when no event is set). regevnevn indicates the priority level of the current interrupts. regevnevn and regevnpriority ?s values are dependent upon the memorized state of the events (as reflected in flags in regevn ). 9.3 register map pos. regevn rw reset function 7 regevn[7] r c1 0 resetsystem event #7 (high priority) clear event #7 when written 1 6 regevn[6] r c1 0 resetsystem event #6 (high priority) clear event #6 when written 1 5 regevn[5] r c1 0 resetsystem event #5 (high priority) clear event #5 when written 1 4 regevn[4] r c1 0 resetsystem event #4 (high priority) clear event #4 when written 1 3 regevn[3] r c1 0 resetsystem event #3 (low priority) clear event #3 when written 1 2 regevn[2] r c1 0 resetsystem event #2 (low priority) clear event #2 when written 1 1 regevn[1] r c1 0 resetsystem event #1 (low priority) clear event #1 when written 1 0 regevn[0] r c1 0 resetsystem event #0 (low priority) clear event #0 when written 1 table 9-1: regevn
9-3 d0304-60 datasheet xe88lc01/01a pos. regevnen rw reset function 7 regevnen[7] rw 0 resetsystem 1= enable event #7 6 regevnen[6] rw 0 resetsystem 1= enable event #6 5 regevnen[5] rw 0 resetsystem 1= enable event #5 4 regevnen[4] rw 0 resetsystem 1= enable event #4 3 regevnen[3] rw 0 resetsystem 1= enable event #3 2 regevnen[2] rw 0 resetsystem 1= enable event #2 1 regevnen[1] rw 0 resetsystem 1= enable event #1 0 regevnen[0] rw 0 resetsystem 1= enable event #0 table 9-2: regevnen pos. regevnpriority rw reset function 7-0 regevnpriority r 11111111 resetsystem code of highest event set table 9-3: regevnpriority pos. regevnevn rw reset function 7-2 - r 00000 unused 1 evnhig r 0 resetsystem one or mo re high priority event is set 0 evnlow r 0 resetsystem one or more low priority event is set table 9-4: regevnevn
10-1 reg_ff - 1.0 ? 28 august 2002 d0304-60 datasheet xe88lc01/01a 10 low power ram 10.1 features 10-2 10.2 overview 10-2 10.3 register map 10-2
10-2 d0304-60 datasheet xe88lc01/01a 10.1 features ? low power ram locations. 10.2 overview in order to save power consumption, 8 8-bit regi sters are provided in page 0. these memory locations should be reserved for often-updated variables. accessi ng these register locations requires much less power than the other general purpose ram locations. 10.3 register map pos. reg00 rw reset function 7-0 reg00 rw xxxxxxxx low-power data memory table 10-1: reg00 pos. reg01 rw reset function 7-0 reg01 rw xxxxxxxx low-power data memory table 10-2: reg01 pos. reg02 rw reset function 7-0 reg02 rw xxxxxxxx low-power data memory table 10-3: reg02 pos. reg03 rw reset function 7-0 reg03 rw xxxxxxxx low-power data memory table 10-4: reg03 pos. reg04 rw reset function 7-0 reg04 rw xxxxxxxx low-power data memory table 10-5: reg04 pos. reg05 rw reset function 7-0 reg05 rw xxxxxxxx low-power data memory table 10-6: reg05 pos. reg06 rw reset function 7-0 reg06 rw xxxxxxxx low-power data memory table 10-7: reg06 pos. reg07 rw reset function 7-0 reg07 rw xxxxxxxx low-power data memory table 10-8: reg07
11-1 pa_ff - 1.0 ? 16 may 2002 d0304-60 datasheet xe88lc01/01a 11 port a 11.1 features 11-2 11.2 overview 11-2 11.3 register map 11-3 11.4 interrupts and events map 11-4 11.5 port a (pa) operation 11-4 11.6 port a electrical specification 11-5
11-2 d0304-60 datasheet xe88lc01/01a 11.1 features ? input port, 8 bits wide ? each bit can be set individually for debounced or direct input ? each bit can be set individually for pull-up or not ? each bit is an interrupt request source on the rising or falling edge ? a system reset can be generated on an input pattern ? pa[0] and pa[1] can generate two events for the cpu, individually maskable ? pa[0] to pa[3] can be used as clock input s for the counters/timers/pwm (product dependent) ? pa[0] can be used to enable the rc oscillator 11.2 overview port a is a general purpose 8 bit wide digital input port, with interrupt capability. figure 11-1 shows its structure. figure 11-1:structure of port a vbat 1 0 resetfromporta 8x regpapullup regpadebounce regpain regpactrl regpaedge regpares1 regpares0 0 1 8x 1 00 01 11 10 0 interrupts events cntclocks 8 8 8 8 8 debounce 10 debfast (regsysmisc(2)) 256 hz 8 khz 8 8 8 port a 8x pareset[x] rc
11-3 d0304-60 datasheet xe88lc01/01a 11.3 register map there are six registers in the port a (pa), namely regpain , regpadebounce , regpaedge , regpapullup , regpares0 and regpares1 . table 11-1 to table 11-6 show the mapping of control bits and functionality. pos. regpain rw reset description 7:0 pain[7:0] r pad pa[7] to pa[0] input value table 11-1: regpain pos. regpadebounce rw reset description 7:0 padebounce[7:0] r w 00000000 resetpconf pa[7] to pa[0] 1: debounce enabled 0: debounce disabled table 11-2: regpadebounce pos. regpaedge rw reset description 7:0 paedge[7:0] r w 00000000 resetsystem pa[7] to pa[0] edge configuration 0: positive edge 1: negative edge table 11-3: regpaedge pos. regpapullup rw reset description 7:0 papullup[7:0] r w 00000000 resetpconf pa[7] to pa[0] pullup enable 0: pullup disabled 1: pullup enabled table 11-4: regpapullup pos. regpares0 rw reset description 7:0 pares0[7:0] r w 00000000 resetsystem pa[7] to pa[0] reset configuration table 11-5: regpares0 pos. regpares1 rw reset description 7:0 pares1[7:0] r w 00000000 resetsystem pa[7] to pa[0] reset configuration table 11-6: regpares
11-4 d0304-60 datasheet xe88lc01/01a 11.4 interrupts and events map interrupt source default mapping in the interrupt manager default mapping in the event manager pa_irqbus[5] regirqmid[5] pa_irqbus[4] regirqmid[4] pa_irqbus[1] regirqmid[1] regevn[4] pa_irqbus[0] regirqmid[0] regevn[0] pa_irqbus[7] regirqlow[7] pa_irqbus[6] regirqlow[6] pa_irqbus[3] regirqlow[3] pa_irqbus[2] regirqlow[2] 11.5 port a (pa) operation the port a input status (debounced or not) can be read from regpain . debounce mode: each bit in port a can be individually debounced by setting the corresponding bit in regpadebounce . after reset, the debounce function is di sabled. after enabling the debouncer, the change of the input value is accepted only if the input value is identical at two consecutive sampling on the rising edge of the selected clock. se lection of the clock is done by the bit debfast in register regsysmisc (see clock block documentation for more precision on the frequency). debfast clock filter 0 256 hz 1 8 khz table 11-7: debounce frequency selection figure 11-2: digital debouncer pull-ups: when the corresponding bit in regpapullup is set to 0, the inputs are floating (pull-up resistors are disconnected). when the corresponding bit in regpapullup is set to 1, a pull-up resistor is connected to the input pin. port a starts up with the pull-up resistors disconnected. port a as an interrupt source: each port a input is an interrupt request sour ce and can be set on rising or falling edge with the corresponding bit in regpaedge . after reset, the rising edge is selected for interrupt generation by default. the interrupt source can be debounced by setting register regpadebounce . note: care must be taken when modifying regpaedge because this register performs an edge selection. the change of this register may result in a transition which may be interpreted as a valid interruption. input ckdebounce debounced 112 1 12
11-5 d0304-60 datasheet xe88lc01/01a port a as an event source: the interrupt signals of the pins pa[0] and pa[1] are also available as events on the event controller. porta as a clock source (product dependent): images of the pa[0] to pa[3] input ports (debounced or not) are available as clock sources for the counter/timer/pwm peripheral (see the counter block documentation for more information). port a as a reset source: port a can be used to generate a system reset by placing a predetermined word on port a externally. the reset is built using a logical and of the 8 pares[x] signals: resetfromporta = pareset[7] and pareset[6 ] and pareset[5] and ... and pareset[0] pareset[x] is itself a logical function of the corre sponding pin pa[x]. one of four logical functions can be selected for each pin by writing into two registers regpares0 and regpares1 as shown in table 11-8. pares1[x] pares0[x] pareset[x] 0 0 0 0 1 pa[x] 1 0 not(pa[x]) 1 1 1 table 11-8: selection bits for reset signal a reset from port a can be inhibited by placing a 0 on both pares1[x] and pares0[x] for at least 1 pin. setting both pares1[x] and pares0[x] to 1, makes the reset independent of the value on the corresponding pin. setting both registers to hff, will reset the circuit independent from the port a input value. this makes it possible to do a reset by software. note: depending of the value of pa[0] to pa[7], the change of regpares0 and regpares1 can cause a reset. therefore it is safe to have alwa ys one (regpares0[x], reg pares1[x]) equal to ?00? during the setting operations. port a as a rc enable: pa[0] can be used to enable the rc oscillator. when rconpa0 bit in regsysmisc is set to 1 and the value of pa[0] (debounced or not) is equal to 1, the enrc bit in regsysclock is automatically set to 1. 11.6 port a electrical specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.5 pf note 1 note 1: this value is indicative only since it depends on the package. table 11-9. port a elec trical specification.
12-1 pb_ff - 1.0 ? 02 september 2002 d0304-60 datasheet xe88lc01/01a 12 port b 12.1 features 12-2 12.2 overview 12-2 12.3 register map 12-2 12.4 port b capabilities 12-3 12.5 port b analog capability 12-3 12.5.1 port b analog configuration 12-3 12.5.2 port b analog function specification 12-4 12.6 port b function capability 12-4 12.7 port b digital capabilities 12-5 12.7.1 port b digital configuration 12-5 12.7.2 port b digital function specification 12-6
12-2 d0304-60 datasheet xe88lc01/01a 12.1 features ? input / output / analog port, 8 bits wide ? each bit can be set individually for input or output ? each bit can be set individually for open-drain or push-pull ? each bit can be set individually for pull- up or not (for input or open-drain mode) ? in open-drain mode, pull-up is not acti ve when corresponding pad is set to zero ? the 8 pads can be connected by pairs to f our internal analog lines (4 line analog bus) ? two internal freq. (cpuck and 32 khz) can be output on pb[2] and pb[3] product dependant: ? two pwm signals can be outputted on the pads pb[0] and pb[1] ? the synchronous serial interfac e (usrt) uses pads pb[5], pb[4] ? the uart interface uses pads pb[6] and pb[7] for tx and rx 12.2 overview port b is a multi-purpose 8 bit input/output port. in addition to digital functions, all pins can be used for analog signals. all port terminals can be selected by pairs as digital input or output or as analog sharing one of four possible analog lines. 12.3 register map pos. regpbout rw reset description in digital mode description in analog mode 7 ? 0 pbout[7-0] r w 0 resetpconf pad pb[7-0] output value analog bus selection for pad pb[7-0] table 12-1: regpbout pos. regpbin rw reset description in digital mode description in analog mode 7 ? 0 pbin[7-0] r w pad pb[7-0] input status unused table 12-2: regpbin pos. regpbdir rw reset description in digital mode description in analog mode 7 ? 0 pbdir [7-0] r w 0 resetpconf pad pb[7-0] di rection (0=input) analog bus selection for pad pb[7-0] table 12-3 : regpbdir pos. regpbopen rw reset description in digital mode description in analog mode 7 ? 0 pbopen[7-0] r w 0 resetpconf pad pb[7-0] open drain (1 = open drain) unused table 12-4: regpbopen pos. regpbpullup rw reset description in digital mode description in analog mode 7 ?0 pbpullup[7] r w 0 resetpconf pull-up for pad pb[7-0] (1=active) connect pad pb[7-0] on selected ana bus table 12-5: regpbpullup pos. regpbana rw reset description in digital mode description in analog mode 7 ? 4 -- r 0000 unused unused 3 pbana [3] r w 0 resetpconf set pb[7:6] in analog mode set pb[7:6] in analog mode 2 pbana [2] r w 0 resetpconf set pb[5:4] in analog mode set pb[5:4] in analog mode 1 pbana [1] r w 0 resetpconf set pb[3:2] in analog mode set pb[3:2] in analog mode 0 pbana [0] r w 0 resetpconf set pb[1:0] in analog mode set pb[1:0] in analog mode table 12-6: regpbana
12-3 d0304-60 datasheet xe88lc01/01a note: depending on the status of the enrespconf bit in regsysctrl , the reset conditions of the registers are different. see the reset block document ation for more details on the resetpconf signal. 12.4 port b capabilities port b usage (priority) name analog (high) functions (medium) digital (low) (default) pb[7] uart rx i/o pb[6] analog uart tx i/o pb[5] usrt s1 i/o pb[4] analog usrt s0 i/o pb[3] 32 khz i/o pb[2] analog clock cpu i/o pb[1] pwm1 counter c (c+d) i/o pb[0] analog pwm0 counter a (a+b) i/o table 12-7: different port b functionality table 12-7 shows the different usage that can be made of port b with the order of priority. if a pair of pins is selected to be analog, it ov erwrites the function and digital set- up. if the pin is not selected as analog, but a function is enabled, it overwrites the digital set-up. if neither the analog nor function are selected for a pin, it is used as an ordinary digital i/o. this is the default configuration at start-up. 12.5 port b analog capability 12.5.1 port b analog configuration port b terminals can be attached to a 4 line analog bus by setting the pbana[x] bits to 1 in the regpbana register. the other registers then define the connection of these 4 analog lines to the different pads of port b. this can be used to implement a simple lcd driver or a/d converter. analog switching is available only when the circuit is powered with sufficient volt age (see specification below). below the specified supply voltage, only voltages that are close to vss or vbat can be switched. when pbana[x] is set to 1, a pair of port b terminals is switched from digital i/o mode to analog mode. the usage of the registers regpbpullup , regpbout and regpbdir define the analog configuration (see table 12-8). when pbana[x] = 1 , then pbpullup[x] connects the pin to the analog bus. pbdir[x] and pbpout[x] select which of the 4 analog lines is used. for odd val ues of x, the selection bits are in the register regpbout (see table 12-8). for even values of x, the selection bits are in the register regpbdir (see table 12-9). if x is odd, pbout[x, x-1] pbpullup[x] pb[x] selection on 00 1 analog line 0 01 1 analog line 1 10 1 analog line 2 11 1 analog line 3 xx 0 high impedance table 12-8: selection of the analog lines for pb[x] when x is odd and pbana[x] = 1
12-4 d0304-60 datasheet xe88lc01/01a if x is even, pbdir[x+1, x] pbpullup[x] pb[x] selection on 00 1 analog line 0 01 1 analog line 1 10 1 analog line 2 11 1 analog line 3 xx 0 high impedance table 12-9: selection of the analog lines for pb[x] when x is even and pbana[x] = 1 example: set the pads pb[2] and pb[3] on the analog line 3. (the values x depend on the configuration of others pads) - apply high impedance in the analog mode (move regpbpullup,#0bxxxx00xx) - go to analog mode (move regpbana,#0bxxxxxx1x) - select the analog line3 (move regpbdir,#0bxxxx11xx and move regpbout,#0bxxxx11xx) - connect the analog line to the pins (move regpbpullup,#0bxxxx11xx) 12.5.2 port b analog function specification the table below defines the on-resistance of t he switches between the pin and the analog bus for different conditions. the series resistance between 2 pins of port b connected to the same analog line is twice the resistance given in the table. sym description min typ max unit comments ron switch resistance 11 k ? note 1 ron switch resistance 15 k ? note 2 cin input capacitance (off) 3.5 pf note 3 cin input capacitance (on) 4.5 pf note 4 table 12-10. analog input specifications. note 1: this is the series resistance betw een the pad and the analog line in 2 cases 1. vbat 2.4v and the vmult peripheral is present on the circuit and enabled. 2. vbat 3.0v and the vmult peripheral is not present on the circuit. note 2: this is the series resistance in case vbat 2.8v and the peripheral vmult is not present on the circuit. note 3: this is the input capacitance seen on the pin when the pin is not connected to an analog line. this value is indicative only si nce it is product and package dependent. note 4: this is the input capacitance seen on the pi n when the pin is connected to an analog line and no other pin is connected to the same analog line. this value is indicative only since it is product and package dependent. 12.6 port b function capability the port b can be used for different functions implemented by other peripherals. the description below is applicable only in so far the circuit contains these peripherals. when the counters are used to implement a pwm f unction (see the documentation of the counters), the pb[0] and pb[1] terminals are us ed as outputs (pb[0] is used if cntpwm0 in regcntconfig1 is set to 1, pb[1] is used if cntpwm1 in regcntconfig1 is set to 1) and the pwm generated values overwrite the values written in regpbout . however, pbdir(0) and pbdir(1) are not automatically overwritten and have to be set to 1.
12-5 d0304-60 datasheet xe88lc01/01a if outputckxtal is set in regsysmisc , the xtal clock is output on pb[ 3] (enablextal in regsysclock must be set to 1). this overrides the value contained in pbout(3) . however, pbdir(3) must be set to 1. the duty cycle of the clock signal is about 50%. similarly, if outputckcpu is set in regsysmisc , the cpu frequency is output on pb[2]. this overrides the value contained in pbout(2) . however, pbdir(2) must be set to 1. the frequency of the cpu clock depends on the selection of the cpusel bit in the regsysclock register (see clock_gen_ff). pins pb[5] and pb[4] can be used for s1 and s0 of the usrt (see usrt documentation) when the usrtenable bit is set in regusrtctrl . the pb[5] and pb[4] then become open-drain. this overrides the values contained in pbopen(5:4) , pbout(5:4) and pbdir(5:4) . if there is no external pull-up resistor on these pins, internal pull-ups should be selected by setting pbpullup(5:4) . when s0 is an output, the pin pb[4] takes the value of usrts0 in regursts0 . when s1 is an output, the pin pb[5] takes the value of usrts1 in regursts1 . pins pb[6] and pb[7] can be used by t he uart (see uart documentation). when uartentx in reguartctrl is set to 1, pb[6] is us ed as output signal tx. when uartenrx in reguartctrl is set to 1, pb[7] is used as input signal rx. this overrides the values contained in pbout(7:6) and pbdir(7:6) . 12.7 port b digital capabilities 12.7.1 port b digital configuration the direction of each bit within port b (input onl y or input/output) can be individually set using the regpbdir register. if pbdir[x] = 1, both the input and output buffe r are active on the corresponding port b. if pbdir[x] = 0, the corresponding port b pin is an i nput only and the output buffer is in high impedance. after reset (resetpconf) port b is in input only mode (pbdir[x] are reset to 0). the input values of port b are available in regpbin (read only). reading is always direct - there is no debounce function in port b. in case of possibl e noise on input signals, a software debouncer with polling or an external hardware filter have to be rea lized. the input buffer is also active when the port is defined as output and allows to read back the effective value on the pin. data stored in regpbout are output at port b if pbdir[x] is 1. the default value after reset is low (0). when a pin is in output mode ( pbdir[x] is set to 1), the output can be a conventional cmos (push- pull) or a n-channel open-drain, driving the output only low. by default, after reset (resetpconf) the pbopen[x] in regpbopen is cleared to 0 (push-pull). if pbopen[x] in regpbopen is set to 1 then the internal p transistor in the output buffer is electrically removed and the output can only be driven low ( pbout[x] =0). when pbout[x] =1, the pin is high impedance. the internal pull-up or an external pull-up resistor can be used to drive the pin high. note: because the p transistor actually exists (this is not a real open-drain output) the pull-up range is limited to vdd + 0.2v (avoid fo rward bias the p transistor / diode). each bit can be set individually for pull-up or not using register regpbpullup . input is pulled up when its corresponding bit in this register is set to 1. default status after (resetpconf) is 0, which means without pull up. to limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an n-channel open-drai n output with the pad set to 1. in the other cases (push-pull output or open-drain output driven low) , the pull up resistors are disabled independent of the value in regpbpullup . after power-on reset, the port b is conf igured as an input port without pull-up.
12-6 d0304-60 datasheet xe88lc01/01a the input buffer is always active, except in analog mode. this means that the port b input should be a valid digital value at all times unless the pin is set in analog mode. violating this rule may lead to high power consumption. 12.7.2 port b digital function specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma r pu pull-up resistance 20 50 80 k ? cin input capacitance 3.5 pf note 1 note 1: this value is indicative only since it depends on the package.
13-1 pc_ff - 1.0 ? 29 august 2002 d0304-60 datasheet xe88lc01/01a 13 port c 13.1 features 13-2 13.2 overview 13-2 13.3 port c (pc) operation 13-2 13.4 register map 13-2 13.5 port c electrical specification 13-3
13-2 d0304-60 datasheet xe88lc01/01a 13.1 features ? input / output port, 8 bits wide ? each bit can be set individually for input or output 13.2 overview port c (pc) is a general purpose 8 bit input/output digital port. figure 13-1 shows its structure. figure 13-1 : structure of port c 13.3 port c (pc) operation the direction of each bit within port c (input or output) can be individually set by using the regpcdir register. if pcdir[x] = 1, the corresponding port c pin becomes an output. after reset, port c is in input mode ( pcdir[x] are reset to 0). output mode: data is stored in regpcout prior to output at port c. input mode: the status of port c is available in regpcin (read only). reading is always direct - there is no digital debounce function associated with port c. in case of possible noise on input signals, a software debouncer or an external filter must be realized. by default after reset, port c is configured as an input port. 13.4 register map there are three registers in the port c (pc), namely regpcin , regpcout and regpcdir . table 13-1 to table 13-3 show the mapping of control bits and functionality of these registers. pos. regpcin rw reset description 7-0 pcin r - pad pc input value table 13-1 regpcin regpcin regpcout regpcdir 8 8 8 port c
13-3 d0304-60 datasheet xe88lc01/01a pos. regpcout rw reset description 7-0 pcout r w 0 resetpconf pad pc output value table 13-2 regpcout pos. regpcdir rw reset description 7-0 pcdir r w 0 resetpconf pad pc direction (0=input) table 13-3 regpcdir 13.5 port c electri cal specification sym description min typ max unit comments v inh input high voltage 0.7*vbat vbat v vbat 2.4v v inl input low voltage vss 0.2*vbat v vbat 2.4v v oh output high voltage vbat-0.4 vbat v vbat=1.2v, i oh =0.3ma vbat=2.4v, i oh =5.0ma vbat=4.5v, i oh =8.0ma v ol output low voltage vss vss+0.4 v vbat=1.2v, i ol =0.3ma vbat=2.4v, i ol =12.0ma vbat=4.5v, i ol =15.0ma cin input capacitance 3.0 pf note 1 note 1: this value is indicative only since it depends on the package. table 13-4. port c electrical specification
14-1 uart_ff - 1.0 ? 05 september 2002 d0304-60 datasheet xe88lc01/01a 14 uart 14.1 features 14-2 14.2 overview 14-2 14.3 registers map 14-2 14.4 interrupts map 14-3 14.5 uart baud rate selection 14-3 14.5.1 uart on the rc oscillator 14-3 14.5.2 uart on the crystal oscillator 14-4 14.6 function description 14-4 14.6.1 configuration bits 14-4 14.6.2 transmission 14-5 14.6.3 reception 14-6 14.7 interrupt or polling 14-6 14.8 software hints 14-7
14-2 d0304-60 datasheet xe88lc01/01a 14.1 features ? full duplex operation with buffered receiver and transmitter. ? internal baud rate generator with 12 programmable baud rates (300 - 115200). ? 7 or 8 bits word length. ? even, odd, or no-parity bit generation and detection ? 1 stop bit ? error receive detection: start, parity, frame and overrun ? receiver echo mode ? 2 interrupts (receive full and transmit empty) ? enable receive and/or transmit ? invert pad rx and/or tx 14.2 overview the uart pins are pb[7], which is used as rx - receive and pb[6] as tx - transmit. 14.3 registers map pos. reguartcmd rw reset description 7 selxtal rw 0 resetsystem select input clock: 0 = rc/external, 1 = xtal 6 uartenrx2 rw 0 resetsystem enable uart reception 5-3 uartrcsel(2:0) rw 000 resetsystem rc prescaler selection 2 uartpm rw 0 resetsystem select parity mode: 0 = odd, 1 = even 1 uartpe rw 0 resetsystem enable parity: 1 = with parity, 0 = no parity 0 uartwl rw 1 resetsystem select word length: 1 = 8 bits, 0 = 7 bits table 14-1: reguartcmd pos. reguartctrl rw reset description 7 uartecho rw 0 resetsystem enable echo mode: 1 = echo rx->tx, 0 = no echo 6 uartenrx1 rw 0 resetsystem enable uart reception 5 uartentx rw 0 resetsystem enable uart transmission 4 uartxrx rw 0 resetsystem invert pad rx 3 uartxtx rw 0 resetsystem invert pad tx 2-0 uartbr(2:0) rw 101 resetsystem select baud rate table 14-2: reguartctrl pos. reguarttx rw reset description 7-0 uarttx rw 00000000 resetsystem data to be sent table 14-3: reguarttx
14-3 d0304-60 datasheet xe88lc01/01a pos. reguarttxsta rw reset description 7-2 - r 000000 unused 1 uarttxbusy r 0 resetsystem uart busy transmitting 0 uarttxfull r 0 resetsystem reguarttx full set by writing to reguarttx cleared when transferring reguarttx into internal shift register table 14-4: reguarttxsta pos. reguartrx rw reset description 7-0 uartrx r 00000000 resetsystem received data table 14-5: reguartrx pos. reguartrxsta rw reset description 7-6 - r 00 unused 5 uartrxserr r 0 resetsystem start error 4 uartrxperr r 0 resetsystem parity error 3 uartrxferr r 0 resetsystem frame error 2 uartrxoerr rc 0 resetsystem overrun error cleared by writing reguartrxsta 1 uartrxbusy r 0 resetsystem uart busy receiving 0 uartrxfull r 0 resetsystem reguartrx full cleared by reading reguartrx table 14-6: reguartrxsta 14.4 interrupts map interrupt source default mapping in the interrupt manager irq_uart_tx irqhig(1) irq_uart_rx irqhig(0) table 14-7: interrupts map 14.5 uart baud rate selection in order to have correct baud rates, the uart inte rface has to be fed with a stable and trimmed clock source. the clock source can be the rc oscillator or the crystal oscillator. the precision of the baud rate will depend on the precision of the selected clock source. 14.5.1 uart on the rc oscillator to select the rc oscillator for the uart, the bit selxtal in reguartcmd has to be 0. in order to obtain a correct baud rate, the rc oscillator frequency has to be set to one of the frequencies given in the table below. the precision of the obtained baud rate is directly proportional to the frequency deviation with respect to the values in the table.
14-4 d0304-60 datasheet xe88lc01/01a frequency selection for correct uart baud rate with rc oscillator (hz) 2?457?600 1?843?200 1?228?800 614?400 for each of these frequencies, the baud ra te can be selected with the bits uartbr(2:0) in reguartctrl and uartrcsel(2:0) in reguartcmd as shown in table 14-8 rc frequency (hz) 2?457?600 1?228?800 614?400 1?843?200 uartrcsel 010 001 000 000 111 38400 115200 110 19200 57600 101 9600 28800 uartbr 100 not possible 4800 14400 table 14-8: uart baud rate with rc clock note: the precision of the baud rate is directly proportional to the frequency deviation of the used clock from the ideal frequency given in the table. in order to increase the precision and stability of the rc oscillator, the dfll (digital frequency locked loop) can be used with the crystal oscillator as a reference. 14.5.2 uart on the crystal oscillator in order to use the crystal oscillator as the clock source for the uart, the bit selxtal in reguartcmd has to be set. the crystal oscillator has to be enabled by setting the enablextal bit in regsysclock . the baud rate selection is done using the uartbr and uartrcsel bits as shown in table 14-9. xtal freq. (hz) uartrcsel uartbr baud rate 011 2400 010 1200 001 600 32768 001 000 300 table 14-9: uart baud rate with xtal clock due to the odd ratio between the crystal o scillator frequency and the baud rate, the generated baud rate has a systematic error of ?2.48%. 14.6 function description 14.6.1 configuration bits the configuration bits of the uart seri al interface can be found in the registers reguartcmd and reguartctrl . the bit selxtal is used to select the clock source (see chapter 14.5). the bits uartselrc and uartbr select the baud rate (see chapter 14.5). the bit uartentx is used to enable or disable the transmission.
14-5 d0304-60 datasheet xe88lc01/01a the bits uartenrx1 and uartenrx2 are used to enable or disable the reception. when one is set to 1, the reception is enabled. the word length (7 or 8 data bits) can be chosen with uartwl . a parity bit is added during transmission or checked during reception if uartpe is set. the parity mode (odd or even) can be chosen with uartpm . setting the bits uartxrx and uartxtx inverts the rx respectively tx signals. the bit uartecho is used to send the received data automat ically back. the transmission function becomes then: tx = rx xor uartxtx . 14.6.2 transmission in order to send data, the transmitter has to be enabled by setting the bit uartentx . data to be sent has to be written to the register reguarttx . the bit uarttxfull in reguarttxsta then goes to 1, indicating to the transmitter that a new word is available. as soon as the transmitter has finished sending the previous word, it then l oads the contents of the register reguarttx to an internal shift register and clears the uarttxfull bit. an interrupt is generated on irq_uart_tx at the falling edge of the uarttxfull bit. the bit uarttxbusy in reguarttxsta shows that the transmitter is busy transmitting a word. a timing diagram is shown in figur e 14-1. data are sent lsb first. new data should be written to the register reguarttx only while uarttxfull is 0, otherwise data will be lost. as y nchronous transmission write to re g uarttx re g uarttx word 1 reguarttx_shift word 1 shift clock tx start b0 b1 b6/7 parity stop uarttxbus y uarttxfull irq_uart_tx as y nchronous transmission ( back to back ) word 1 word 2 write to re g uarttx re g uarttx word 1 word 2 reguarttx_shift word 1 word 2 shift clock tx start b0 b6/7 stop start uarttxbus y uarttxfull irq_uart_tx figure 14-1. uart transmission timing diagram.
14-6 d0304-60 datasheet xe88lc01/01a 14.6.3 reception on detection of the start bit, the uartrxbusy bit is set. on detection of the stop bit, the received data are transferred from the internal shift register to the register reguartrx . at the same time, the uartrxfull bit is set and an interrupt is generated on ir q_uart_rx. this indicates that new data is available in reguartrx . the timing diagram is shown in figure 14-2. the uartrxfull bit is cleared when reguartrx is read. if the register was not read before the receiver transfers a new word to it, the bit uartrxoerr (overflow error) is set and the previous contents of the register is lost. uartrxoerr is cleared by writing any data to reguartrxsta . the bit uartrxserr is set if a start error has been detected. the bit is updated at data transfer to reguartrx . the bit uartrxperr is set if a parity error has been detected, i.e. the received parity bit is not equal to the calculated parity of the received data. the bit is updated at data transfer to reguartrx . the bit uartrxferr in reguartrxsta shows that a frame error has been detected. no stop bit has been detected. asynchronous reception read of reguartrx (software) reguartrx_shift word 1 reguartrx word 1 shift clock rx start b0 b6/7 parity stop uartrxbusy uartrxfull irq_uart_rx figure 14-2. uart reception timing diagram. 14.7 interrupt or polling the transmission and reception software can be driven by interruption or by polling the status bits. interrupt driven reception: each time an irq_uart_rx in terrupt is generated, a new word is available in reguartrx . the register has to be read before a new word is received. interrupt driven transmission: each time the contents of reguarttx is transferred to the transmission shift register, an irq_uart_tx interrupt is generated. a new word can then be written to reguarttx . reception driven by polling: the uartrxfull bit is to be read and checked. when it is 1, the reguartrx register contains new data and has to be read before a new word is received. transmission driven by polling: the uarttxfull bit is to read and checked. when it is 0, the reguarttx register is empty and a new word can be written to it.
14-7 d0304-60 datasheet xe88lc01/01a 14.8 software hints example of program for a transmission with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. wait until the uarttxfull bit in reguarttxsta register equals 0. 4. jump to 2 to write the next by te if the message is not finished. 5. end of transmission. example of program for a transmission with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart transmission). 2. write a byte to reguarttx . 3. after an interrupt and if the message is not finished, jump to 2 4. end of transmission. example of program for a reception with polling: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. wait until the uartrxfull bit in the reguartrxsta register equals 1. 3. read the reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception. example of program for a reception with interrupt: 1. the reguartcmd register and the reguartctrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable uart reception). 2. when there is an interrupt, jump to 3 3. read reguartrxsta and check if there is no error. 4. read data in reguartrx . 5. if data is not equal to end-of-line, then jump to 2. 6. end of reception.
15-1 usrt_ff - 1.1 ? 30 september 2002 d0304-60 datasheet xe88lc01/01a 15 usrt 15.1 features 15-2 15.2 overview 15-2 15.3 register map 15-2 15.4 interrupts map 15-3 15.5 conditional edge detection 1 15-4 15.6 conditional edge detection 2 15-4 15.7 interrupts or polling 15-4 15.8 function description 15-4
15-2 d0304-60 datasheet xe88lc01/01a 15.1 features the usrt implements a hardware support for software implemented serial protocols: ? control of two external lines s0 and s1 (read/write). ? conditional edge detection generates interrupts. ? s0 rising edge detection. ? s1 value is stored on s0 rising edge. ? s0 signal can be forced to 0 after a falling edge on s0 for clock stretching in the low state. ? s0 signal can be stretched in the low state after a falling edge on s0 and after a s1 conditional detection. 15.2 overview the usrt block supports software universal sync hronous receiver and transmitter mode interfaces. external lines s0 and s1 respectively correspond to clock line and data line. s0 is mapped to pb[4] and s1 to pb[5] when the usrt block is enabled. it is independent from regpbdir (port b can be input or output). when usrt is enabled, the configurations in port b for pb[4] and pb[5] are overwritten by the usrt c onfiguration. internal pull-ups can be used by setting the pbpullup[5:4] bits. conditional edge detections are provided. regusrts1 can be used to read the s1 data line from pb[5] in receive mode or to drive the output s1 line pb[5] by writing it when in transmit mode. it is advised to read s1 data when in receive mode from the regusrtbuffers1 register, which is the s1 value sampled on a rising edge of s0. 15.3 register map block configuration registers: pos. regusrts1 rw reset function 7-1 - r 0000000 unused 0 usrts1 rw 1 resetsystem write: data s1 written to pad pb[5]), read: value on pb[5] (not usrts1 value). table 15-1: regusrts1 pos. regusrts0 rw reset function 7-1 - r 0000000 unused 0 usrts0 rw 1 resetsystem write: clock s0 written to pad pb[4], read: value on pb[4] (not usrts0 value). table 15-2: regusrts0 the values that are read in the registers regusrts1 and regusrts0 are not necessarily the same as the values that were written in the register. the read value is read back on the circuit pins, not in the registers. since the outputs are open drain, a value different from the register value may be forced by an external circuit on the circuit pins.
15-3 d0304-60 datasheet xe88lc01/01a pos. regusrtctrl rw reset function 7-4 - r ?0000? unused 3 usrtwaits0 r 0 resetsystem clock stretching flag (0=no stretching), cleared by writing regusrtbuffers1 2 usrtenwaitcond1 rw 0 resetsystem enable stretching on usrtcond1 detection (0=disable) 1 usrtenwaits0 rw 0 resetsystem enable stretching operation (0=disable) 0 usrtenable rw 0 resetsystem e nable usrt operation (0=disable) table 15-3: regusrtctrl pos. regusrtcond1 rw reset function 7-1 - r 0000000 unused 0 usrtcond1 r/c 0 resetsystem state of condition 1 detection (1 =detected), cleared when written. table 15-4: regusrtcond1 pos. regusrtcond2 rw reset function 7-1 - r 0000000 unused 0 usrtcond2 r/c 0 resetsystem state of condition 2 detection (1 =detected), cleared when written. table 15-5: regusrtcond2 pos. regusrtbuffers1 rw reset function 7-1 - r 0000000 unused r value on s1 at last s0 rising edge. clear regusrtedges0 bit in regusrtedges0 0 usrtbuffers1 w x clear usrtwaits0 bit in regusrtctrl with any value table 15-6: regusrtbuffers1 pos. regusrtedges0 rw reset function 7-1 - r 0000000 unused 0 usrtedges0 r 0 resetsystem st ate of rising edge detection on s0 (1=detected). cleared by reading regusrtbuffers1 table 15-7: regusrtedges0 15.4 interrupts map interrupt source default mapping in the interrupt manager irq_cond1 regirqmid(7) irq_cond2 regirqmid(6) table 15-8: interrupts map
15-4 d0304-60 datasheet xe88lc01/01a 15.5 conditional edge detection 1 s1 s0 figure 15-1: condition 1 condition 1 is satisfied when s0=1 at the falling edge of s1. the bit usrtcond1 in regusrtcond1 is set when the condition 1 is detected and the usrt interface is enabled ( usrtenable =1). condition 1 is asserted for both modes (receiver and transmitter). the usrtcond1 bit is read only and is cleared by all reset conditions and by wr iting any data to its address. condition 1 occurrence also generates an interrupt on irq_cond1. 15.6 conditional edge detection 2 s1 s0 figure 15-2: condition 2 condition 2 is satisfied when s0=1 at the rising edge of s1. the bit usrtcond2 in regusrtcond2 is set when the condition 2 is detected and the usrt interface is enabled. condition 2 is asserted for both modes (receiver and transmitter). the usrtcond2 bit is read only and is cleared by all reset conditions and by writing any data to its address. condition 2 occurrence also generates an interrupt on irq_cond2. 15.7 interrupts or polling in receive mode, there are two possibilities to det ect condition 1 or 2: the detection of the condition can generate an interrupt or the register s can be polled (reading and checking the regusrtcond1 and regusrtcond2 registers for the status of usrt communication). 15.8 function description the bit usrtenable in regusrtctrl is used to enable the usrt inte rface and controls the pb[4] and pb[5] pins. this bit puts these two port b lines in the open drain configuration requested to use the usrt interface.
15-5 d0304-60 datasheet xe88lc01/01a if no external pull-ups are added on pb[4] and pb[5], the user can activate internal pull-ups by setting pbpullup[4] and pbpullup[5] in regpbpullup . the bits usrtenwaits0 , usrtenwaitcond1 , usrtwaits0 in regusrtctrl are used for transmitter/receiver control of usrt interface. figure 15-3 shows the unconditional clock stre tching function which is enabled by setting usrtenwaits0. s0 us r tw ai ts 0 write reg usrtbuffers1 figure 15-3: s0 stretching (usrtenwaits0=1) when usrtenwaits0 is 1, the s0 line will be maintained at 0 after its falling edge (clock stretching). usrtwaits0 is then set to 1, indicating that the s0 line is forced low. one can release s0 by writing to the regusrtbuffers1 register. the same can be done in combination with condition 1 detection by setting the usrtenwaitcond1 bit. figure 15-4 shows the conditional clock stre tching function which is enabled by setting usrtenwaitcond1 . s0 us r tw ai ts 0 write reg usrtbuffers1 s1 figure 15-4: conditional stretching (usrtenwaitcond1=1)
15-6 d0304-60 datasheet xe88lc01/01a when usrtenwaitcond1 is 1, the s0 signal will be stretched in its low state after its falling edge if the condition 1 has been detected before ( usrtcond1 =1). usrtwaits0 is then set to 1, indicating that the s0 line is forced low. one can release s0 by writing to the regusrtbuffers1 register. figure 15-5 shows the sampling function implemented by the usrtbuffers1 bit. the bit usrtbuffers1 in regusrtbuffers1 is the value of s1 sampled on pb[4] at the last rising edge of s0. the bit usrtedges0 in regusrtedges0 is set to one on the same s0 rising edge and is cleared by a read operation of the regusrtbuffers1 register. the bit therefor indicate s that a new value is present in the regusrtbuffers1 which was not yet read. s0 usrtbuffers1 read reg usrtbuffers1 s1 us r t edg e s 0 figure 15-5: s1 sampling
16-1 d0304-60 datasheet xe88lc01 / 01a 16. acquisition chain 16.1 zoomingadc ? featur es ............................................................................................... 16-2 16.2 overview .................................................................................................................. ....... 16-2 16.3 register map .............................................................................................................. .... 16-3 16.4 zoomingadc ? descript ion .......................................................................................... 16-4 16.4.1 acquisi tion c hain ....................................................................................................... ...... 16-4 16.4.2 peripheral registers .................................................................................................... .... 16-6 16.4.3 continuous-time vs. on-r equest ................................................................................... 16-7 16.5 input mu ltipl exers ........................................................................................................ .. 16-9 16.6 programmable gain amplifie rs .................................................................................. 16-10 16.6.1 pga & a dc enablin g .................................................................................................... 16 -11 16.6.2 pga1 .................................................................................................................... ......... 16-12 16.6.3 pga2 .................................................................................................................... ......... 16-12 16.6.4 pga3 .................................................................................................................... ......... 16-12 16.7 adc charact eristics .................................................................................................... 16- 13 16.7.1 conversi on sequence ................................................................................................... 16 -13 16.7.2 sampli ng fre quency ...................................................................................................... 16-14 16.7.3 over-sam pling ra tio ..................................................................................................... 16-14 16.7.4 elementary conversions................................................................................................ 16 -14 16.7.5 resolution .............................................................................................................. ........ 16-15 16.7.6 conversion time & throug hput..................................................................................... 16-16 16.7.7 output code fo rmat ...................................................................................................... 16-16 16.7.8 power sa ving modes..................................................................................................... 1 6-18 16.8 specifications and measured curv es ........................................................................ 16-18 16.8.1 defaul t settings ........................................................................................................ ..... 16-18 16.8.2 specifications.......................................................................................................... ....... 16-19 16.8.3 linearity ............................................................................................................... .......... 16-21 16.8.3.1 integral non-li nearity ................................................................................................ ...... 16-21 16.8.3.2 differentia l non-linearity ............................................................................................ ..... 16-24 16.8.4 noise................................................................................................................... ........... 16-25 16.8.5 gain error an d offset error............................................................................................ 1 6-26 16.8.6 power co nsumption ...................................................................................................... 1 6-27 16.8.7 power supply re jection ratio ....................................................................................... 16-29 16.9 applicat ion hi nts ......................................................................................................... 16-30 16.9.1 input impedance ......................................................................................................... ... 16-30 16.9.2 pga settling or input channel modifi cations ................................................................ 16-30 16.9.3 pga gain & offset, linearity and no ise........................................................................ 16-30 16.9.4 frequency response..................................................................................................... 1 6-31 16.9.5 power reduction ......................................................................................................... .. 16-32
16-2 d0304-60 datasheet xe88lc01 / 01a 16.1 zoomingadc ? features the zoomingadc ? is a complete and versatile low-power analog front-end interface typically intended for sensing applications. the key features of the zoomingadc ? are: programmable 6 to 16-bit dynamic range oversampled adc ? flexible gain programming between 0.5 and 1000 ? flexible and large range offset compensation ? 4-channel differential or 8-channel single-ended input multiplexer ? 2-channel differential reference inputs ? power saving modes ? direct interfacing to coolrisc ? microcontroller 16.2 overview pga1 pga2 pga3 adc mux mux gd1 gd2 gd3 off2 off3 0 1 2 3 4 5 6 7 0 1 2 3 analog inputs 16 v in f s v ref v in,adc gain1 gain2 gain3 offset3 offset2 reference selection input selection zoom reference inputs v d1 v d2 f s figure 16-1. zoomingadc ? general functional block diagram the total acquisition chain consists of an input mu ltiplexer, 3 programmable gain amplifier stages and an oversampled a/d converter. the reference voltage can be selected on two different channels. two offset compensation amplifiers allow for a wide offset compensation range. the programmable gain and offset allow one to zoom in on a small portion of the reference voltage defined input range.
16-3 d0304-60 datasheet xe88lc01 / 01a 16.3 register map there are eight registers in the acquisition chain (ac), namely regacoutlsb , regacoutmsb , regaccfg0 , regaccfg1 , regaccfg2 , regaccfg3 , regaccfg4 and regaccfg5 . table 16-2 to table 16-9 show the mapping of control bits and fu nctionality of these registers while table 16-1 gives an overview of these eight. the register map only gives a short description of the different configuration bits. more detailed information is found in subsequent sections. register name regacoutlsb regacoutmsb regaccfg0 regaccfg1 regaccfg2 regaccfg3 regaccfg4 regaccfg5 table 16-1: ac registers pos. regacoutlsb rw reset description 7:0 out[7:0] r 00000000 resetsystem lsb of the output code table 16-2: regacoutlsb pos. regacoutmsb rw reset description 7:0 out[15:8] r 00000000 resetsystem msb of the output code table 16-3: regacoutmsb pos. regaccfg0 rw reset description 7 start w r0 0 resetsystem starts a conversion 6:5 set_nelconv[1:0] r w 01 resetsystem sets the number of elementary conversions 4:2 set_osr[2:0] r w 010 resetsystem sets the oversampling rate of an elementary conversion 1 cont r w 0 resetsystem continuous conversion mode 0 reserved r w 0 resetsystem table 16-4: regaccfg0 pos. regaccfg1 rw reset description 7:6 ib_amp_adc[1:0] r w 11 resetsystem bias current selection of the adc converter 5:4 ib_amp_pga[1:0] r w 11 resetsystem bi as current selection of the pga stages 3:0 enable[3:0] r w 0000 resetsystem enables the different pga stages and the adc table 16-5: regaccfg1
16-4 d0304-60 datasheet xe88lc01 / 01a pos. regaccfg2 rw reset description 7:6 fin[1:0] r w 00 resetsyste m sampling frequency selection 5:4 pga2_gain[1:0] r w 00 resets ystem pga2 stage gain selection 3:0 pga2_offset[3:0] r w 0000 resetsystem pga2 stage offset selection table 16-6: regaccfg2 pos. regaccfg3 rw reset description 7 pga1_gain r w 0 resetsyste m pga1 stage gain selection 6:0 pga3_gain[6: 0] r w 0000000 resetsystem pga3 stage gain selection table 16-7: regaccfg3 pos. regaccfg4 rw reset description 7 reserved r 0 unused 6:0 pga3_offset[6:0] r w 0000000 resetsystem pga3 stage offset selection table 16-8: regaccfg4 pos. regaccfg5 rw reset description 7 busy r 0 resetsystem activity flag 6 def w r0 0 selects default configuration 5:1 amux[4:0] r w 00000 resetsystem input channel config uration selector 0 vmux r w 0 resetsystem reference channel selector table 16-9: regaccfg5 16.4 zoomingadc ? description figure 16-2 gives a more detailed desc ription of the acquisition chain. 16.4.1 acquisition chain figure 16-1 shows the general bloc k diagram of the acquisition chain (ac). a control block (not shown in figure 16-1) manages all communications with the coolrisc ? microcontroller. analog inputs can be selected among eight input cha nnels, while reference input is selected between two differential channels. the core of the zooming section is made of three differential programmable amplifiers (pga). after selection of a combination of input and reference signals v in and v ref , the input voltage is modulated and amplified through stages 1 to 3. fine gain programming up to 1'000v/v is possible. in addition, the last two stages provide programmable offse t. each amplifier can be bypassed if needed. the output of the pga stages is directly fed to t he analog-to-digital converte r (adc), which converts the signal v in,adc into digital.
16-5 d0304-60 datasheet xe88lc01 / 01a like most adcs intended for instrumentat ion or sensing applications, the zoomingadc ? is an over- sampled converter (see note 1 ). the adc is a so-called incrementa l converter, with bipolar operation (the adc accepts both positive and negative input vo ltages). in first approxim ation, the adc output result relative to full-scale ( fs ) delivers the quantity: 2 / 2 / , ref adc in adc v v fs out ? (eq. 1) in two's complement (see sections 16.4 and 16.7 for details). the output code out adc is - fs /2 to + fs /2 for v in,adc ? - v ref /2 to + v ref /2 respectively. as will be shown in section 16.6, v in,adc is related to input voltage v in by the relationship: ref tot in tot adc in v gdoff v gd v ? ? ? = , (v) (eq. 2) where gd tot is the total pga gain, and gdoff tot is the total pga offset. pga1 pga2 pga3 adc mux register bank acquisition chain gd1 gd2 gd3 off2 off3 0 1 2 3 4 5 6 7 0 1 2 3 ac_a ac_r regacoutlsb regacoutmsb 8 8 sampling frequency f s adc busy flag default settings conversion start nbr of elementary cycles over-sampling ratio continuous vs. on-request power saving modes pga enabling regaccfg5 regaccfg4 regaccfg3 regaccfg2 regaccfg1 regaccfg0 5 2 4 7 7 inputs v in f s v ref v in,adc f s mux figure 16-2. zoomingadc ? detailed functional block diagram 1 note: over-sampled converters are operated with a sampling frequency f s much higher than the input signal's nyquist rate (typically f s is 20-1'000 times the input signal bandwidth). the sampling frequency to throughput ratio is large (typically 10-500). these converters include digital decimati on filtering. they are mainly used for high resolution, and/or low-to-medium speed applications.
16-6 d0304-60 datasheet xe88lc01 / 01a 16.4.2 peripheral registers figure 16-2 shows a detailed functi onal diagram of the zoomingadc ? . in table 16-10 the configuration of the peripheral registers is detailed. the system has a bank of eight 8- bit registers: six registers are used to configure the acquisition chain ( regaccfg0 to 5 ), and two registers are used to store the output code of the analog-to-digital conversion ( regacoutmsb & lsb ). the register coding of the adc parameters and performance characteristics are detailed in section 16.7. table 16-10. peripheral registers to configure the acquisition chain (ac) and to store the analog-to-digital conversion (adc) result bit position register name 7 6 5 4 3 2 1 0 regacoutlsb out[7:0] regacoutmsb out[15:8] regaccfg0 default values: star t 0 set_nelc[1:0] 01 set_osr[2:0] 010 cont 0 test 0 regaccfg1 default values: ib_amp_adc[ 1:0] 11 ib_amp_pga[1: 0] 11 enable[3:0] 0001 regaccfg2 default values: fin[1:0] 00 pga2_gain[1:0] 00 pga2_offset[3:0] 0000 regaccfg3 default values: pga1 _g 0 pga3_gain[6:0] 0000000 regaccfg4 default values: 0 pga3_offset[6:0] 0000000 regaccfg5 default values: busy 0 def 0 amux[4:0] 00000 vmux 0 with: ? out : (r) digital output code of the analog-to-digital converter. (msb = out[15] ) ? start : (w) setting this bit triggers a single conversion (after the current one is finished). this bit always reads back 0. ? set_nelc : (rw) sets the number of elementary conversions to 2 set_nelc[1:0] . to compensate for offsets, the input signal is chopped bet ween elementary conversions (1,2,4,8). ? set_osr : (rw) sets the over-sampling rate ( osr ) of an elementary conversion to 2 (3+set_osr[2:0]) . osr = 8, 16, 32, ..., 512, 1024. ? cont : (rw) setting this bit starts a conversion. a new conver sion will automatically begin as long as the bit remains at 1. ? test : bit only used for test purposes. in normal mode, this bit is forced to 0 and cannot be overwritten. ? ib_amp_adc : (rw) sets the bias current in the adc to 0.25*(1+ ib_amp_adc[1:0] ) of the normal operation current (25, 50, 75 or 100% of nom inal current). to be used for low-power, low- speed operation. ? ib_amp_pga : (rw) sets the bias current in the pgas to 0.25*(1+ ib_amp_pga[1:0] ) of the normal operation current (25, 50, 75 or 100% of nom inal current). to be used for low-power, low- speed operation.
16-7 d0304-60 datasheet xe88lc01 / 01a ? enable : (rw) enables the adc modulator (bit 0) and the di fferent stages of the pgas (pgai by bit i=1,2,3). pga stages that are disabled are bypassed. ? fin : (rw) these bits set the sampling frequency of the acquisition chain. expressed as a fraction of the oscillator frequency, the sampling frequency is given as: 00 ? 1/4 f rc , 01 ? 1/8 f rc , 10 ? 1/32 f rc , 11 ? ~8khz. ? pga1_gain : (rw) sets the gain of the first stage: 0 ? 1, 1 ? 10. ? pga2_gain : (rw) sets the gain of the second stage: 00 ? 1, 01 ? 2, 10 ? 5, 11 ? 10. ? pga3_gain : (rw) sets the gain of the third stage to pga3_gain[6:0] ? 1/12. ? pga2_offset : (rw) sets the offset of the second stage betw een ?1 and +1, with increments of 0.2. the msb gives the sign (0 positive, 1 negative); amplitude is coded with the bits pga2_offset[5:0] . ? pga3_offset : (rw) sets the offset of the third stage betwe en ?5.25 and +5.25, with increments of 1/12. the msb gives the sign (0 positive, 1 negative); amplitude is coded with the bits pga3_offset[5:0] . ? busy : (r) set to 1 if a conversion is running. note that t he flag is set at the effect ive start of the conversion. since the adc is generally synchronized on a lower frequency clock than the cpu, there might be a small delay (max. 1 cycle of the adc sampling frequency) be tween the writing of the st art or cont bits and the appearance of busy flag. ? def : (w) sets all values to their de faults (pga disabled, max speed, nominal modulator bias current, 2 elementary conversions, over-sampling rate of 32) and st arts a new conversion with out waiting the end of the preceding one. ? amux(4:0): (rw) amux[4] sets the mode (0 ? 4 differential inputs, 1 ? 7 inputs with a(0) = common reference) amux(3) sets the sign (0 ? straight, 1 ? cross) amux[2:0] sets the channel. ? vmux : (rw) sets the differential reference channel (0 ? r(1) and r(0) , 1 ? r(3) and r(2) ). (r = read; w = write; rw = read & write) 16.4.3 continuous-time vs. on-request the adc can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit cont ). in "continuous-time" mode, the input signal is repeat edly converted into digital. after a conversion is finished, a new one is automatically initiated. the ne w value is then written in the result register, and the corresponding internal trigger pulse is generated. this operation is sketched in figure 16-3. the conversion time in this case is defined as t conv . internal trig ouput code regacout[15:0] t conv busy irq figure 16-3. adc "continuous-time" operation figure 16-4. adc "on-request" operation internal trig ouput code regacout[15:0] t conv request start busy irq
16-8 d0304-60 datasheet xe88lc01 / 01a in the "on-request" mode, the internal behaviour of the converter is the same as in the "continuous- time" mode, but the conversion is in itiated on user request (with the start bit). as shown in figure 16-4, the conversion time is also t conv . note that the flag is set at the effective start of the conversion. since the adc is generally synchronized on a lowe r frequency clock than t he cpu, there might be a small delay (max. 1 cycle of the adc sampling frequ ency) between the writing of the start or cont bits and the appearance of busy flag.
16-9 d0304-60 datasheet xe88lc01 / 01a 16.5 input multiplexers the zoomingadc ? has eight analog inputs ac_a(0) to ac_a(7) and four reference inputs ac_r(0) to ac_r(3) . let us first define the differential input voltage v in and reference voltage v ref respectively as: inn inp in v v v ? = (v) (eq. 3) and: refn refp ref v v v ? = (v) (eq. 4) as shown in table 16-11 the inputs can be configured in two ways: either as 4 differential channels ( v in1 = ac_a(1) - ac_a(0) ,..., v in4 = ac_a(7) - ac_a(6) ), or ac_a(0) can be used as a common reference, providing 7 signal paths all referred to ac_a(0) . the control word for the analog input selection is amux[4:0] . notice that the bit amux[3] controls the sign of the input voltage. amux[4:0] (regaccfg5[5:1]) v inp v inn amux[4:0] (regaccfg5[5:1]) v inp v inn 00x00 00x01 00x10 00x11 ac_a(1) ac_a(3) ac_a(5) ac_a(7) ac_a(0) ac_a(2) ac_a(4) ac_a(6) 01x00 01x01 01x10 01x11 ac_a(0) ac_a(2) ac_a(4) ac_a(6) ac_a(1) ac_a(3) ac_a(5) ac_a(7) 10000 10001 10010 10011 10100 10101 10110 10111 ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) ac_a(0) 11000 11001 11010 11011 11100 11101 11110 11111 ac_a(0) ac_a(0) ac_a(1) ac_a(2) ac_a(3) ac_a(4) ac_a(5) ac_a(6) ac_a(7) table 16-11. analog input selection similarly, the reference voltage is chosen among two differential channels ( v ref1 = ac_r(1)- ac_r(0) or v ref2 = ac_r(3)-ac_r(2) ) as shown in table 16-12. the selection bit is vmux . the reference inputs v refp and v refn (common-mode) can be up to the power supply range. vmux (regaccfg5[0]) v refp v refn 0 ac_r(1) ac_r(0) 1 ac_r(3) ac_r(2) table 16-12. analog reference input selection
16-10 d0304-60 datasheet xe88lc01 / 01a 16.6 programmable gain amplifiers as seen in figure 16-1, the zooming function is implemented with three programmable gain amplifiers (pga). these are: ? pga1: coarse gain tuning ? pga2: medium gain and offset tuning ? pga3: fine gain and offset tuning all gain and offset settings are realized with ratios of capacitors. the user has control over each pga activation and gain, as well as the offset of stages 2 and 3. these functions are examined hereafter. enable[3:0] block xxx0 xxx1 adc disabled adc enabled xx0x xx1x pga1 disabled pga1 enabled x0xx x1xx pga2 disabled pga2 enabled 0xxx 1xxx pga3 disabled pga3 enabled table 16-13 adc & pga enabling pga1_gain pga1 gain gd 1 (v/v) 0 1 1 10 table 16-14 pga1 gain settings pga2_gain[1:0] pga2 gain gd 2 (v/v) 00 1 01 2 10 5 11 10 table 16-15 pga2 gain settings pga2_offset[3:0] pga2 offset gdoff 2 (v/v) 0000 0 0001 +0.2 0010 +0.4 0011 +0.6 0100 +0.8 0101 +1 1001 -0.2 1010 -0.4 1011 -0.6 1100 -0.8 1101 -1 table 16-16 pga2 offset settings
16-11 d0304-60 datasheet xe88lc01 / 01a pga3_gain[6:0] pga3 gain gd 3 (v/v) 0000000 0 0000001 1/12(=0.083) ... ... 0000110 6/12 ... ... 0001100 12/12 0010000 16/12 ... 0100000 32/12 ... 1000000 64/12 ... 1111111 127/12(=10.58) table 16-17 pga3 gain settings pga3_offset[6:0] pga3 offset gdoff 3 (v/v) 0000000 0 0000001 +1/12(=+0.083) 0000010 +2/12 ... ... 0010000 +16/12 ... ... 0100000 +32/12 ... ... 0111111 +63/12(=+5.25) 1000000 0 1000001 -1/12(=-0.083) 1000010 -2/12 ... ... 1010000 -16/12 ... ... 1100000 -32/12 ... ... 1111111 -63/12(=-5.25) table 16-18 pga3 offset settings 16.6.1 pga & adc enabling depending on the application objectives, the user may enable or bypass each pga stage. this is done according to the word enable and the coding given in table 16-13. to reduce power dissipation, the adc can also be inactivated while idle.
16-12 d0304-60 datasheet xe88lc01 / 01a 16.6.2 pga1 the first stage can have a buffer function (unity gai n) or provide a gain of 10 (see table 16-14). the voltage v d1 at the output of pga1 is: in d v gd v ? = 1 1 (v) (eq. 5) where gd 1 is the gain of pga1 (in v/v) controlled with the bit pga1_gain . 16.6.3 pga2 the second pga has a finer gain and offset tuning capability, as shown in table 16-15 and table 16-16. the voltage v d2 at the output of pga2 is given by: ref d d v gdoff v gd v ? ? ? = 2 1 2 2 (v) (eq. 6) where gd 2 and gdoff 2 are respectively the gain and offset of pga2 (in v/v). these are controlled with the words pga2_gain[1:0] and pga2_offset[3:0] . as shown in equation 6, the offset correction is direct ly proportional to the reference voltage. all drifts and perturbations on the reference voltage will affe ct the precision of the offset compensation. 16.6.4 pga3 the finest gain and offset tuning is performed with the third and last pga stage, according to the coding of table 16-17 and table 16-18. the output of pga3 is also the input of the adc. thus, similarly to pga2, we find that the voltage entering the adc is given by: ref d adc in v gdoff v gd v ? ? ? = 3 2 3 , (v) (eq. 7) where gd 3 and gdoff 3 are respectively the gain and offset of pga3 (in v/v). the control words are pga3_gain[6:0] and pga3_offset[6:0] . to remain within the signal compliance of the pga stages, the condition: dd d d v v v < 2 1 , (v) (eq. 8) must be verified. as shown in equation 7, the offset correction is direct ly proportional to the reference voltage. all drifts and perturbations on the reference voltage will affe ct the precision of the offset compensation. finally, combining equations eq. 5 to eq. 7 for the three pga stages, the input voltage v in,adc of the adc is related to v in by: ref tot in tot adc in v gdoff v gd v ? ? ? = , (v) (eq. 9) where the total pga gain is defined as: 1 2 3 gd gd gd gd tot ? ? = (v/v) (eq. 10)
16-13 d0304-60 datasheet xe88lc01 / 01a and the total pga offset is: 2 3 3 gdoff gd gdoff gdoff tot ? + = (v/v) (eq. 11) 16.7 adc characteristics the main performance characteristics of the adc (re solution, conversion time, etc.) are determined by three programmable parameters. the setting of these parameters and the resulting performances are described later. ? sampling frequency f s , ? over-sampling ratio osr , and ? number of elementary conversions n elconv . 16.7.1 conversion sequence a conversion is started each time the bit start or the bit def is set. as depicted in figure 16-5, a complete analog-to-digital conversion sequence is made of a set of n elconv elementary incremental conversions and a final quantization step. ea ch elementary conversion is made of ( osr +1) sampling periods t s =1/ f s , i.e.: s elconv f osr t / ) 1 ( + = (s) (eq. 12) the result is the mean of the elementary conversi on results. an important feature is that the elementary conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the other to the out put code. thus, converter internal offset is eliminated if at least two elementar y sequences are performed (i.e. if n elconv 2). a few additional clock cycles are also required to in itiate and end the conversion properly. conversion index offset t elconv = (osr+1)/f s elementary conversion 1 + elementary conversion 2 - elementary conversion n elconv - 1 + elementary conversion n elconv - init end t conv conversion result figure 16-5 analog-to-digital conversion sequence
16-14 d0304-60 datasheet xe88lc01 / 01a 16.7.2 sampling frequency the word fin[1:0] is used to select the sampling frequency f s (table 16-19). three sub-multiples of the internal rc-based frequency f rcext can be chosen. for fin = "11", sampling frequency is about 8khz. additional information on oscillators and their control can be found in the clock block documentation. sampling frequency f s (hz) fin[1:0] lc01/05 lc02 00 1/4 ? f rc 1/8 ? f rcext 01 1/8 ? f rc 1/16 ? f rcext 10 1/32 ? f rc 1/64 ? f rcext 11 8khz 4khz table 16-19 sampling frequency settings ( f rc = rc-based frequency) 16.7.3 over-sampling ratio the over-sampling ratio ( osr ) defines the number of integration cycles per elementary conversion. its value is set with the word set_osr[2:0] in power of 2 steps (see table 16-20) given by: 0] : set_osr[2 3 2 + = osr (-) (eq. 13) set_osr[2:0] (regaccfg0[4:2]) over-sampling ratio osr (-) 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 table 16-20 over-sampling ratio settings 16.7.4 elementary conversions as mentioned previously, the whole conv ersion sequence is made of a set of n elconv elementary incremental conversions. this number is set with the word set_nelc[1:0] in power of 2 steps (see table 16-21) given by: 0] : set_nelc[1 2 = elconv n (-) (eq. 14)
16-15 d0304-60 datasheet xe88lc01 / 01a set_nelc[1:0] (regaccfg0[6:5]) # of elementary conversions n elconv (-) 00 1 01 2 10 4 11 8 table 16-21 number of elementary conversion settings as already mentioned, n elconv must be equal or greater than 2 to reduce internal amplifier offsets. 16.7.5 resolution the theoretical resolution of the adc, wit hout considering thermal noise, is given by: ) ( log ) ( log 2 2 2 elconv n osr n + ? = (bits) (eq. 15) 5 7 9 11 13 15 17 000 001 010 011 100 101 110 111 set _ osr resolution - n [bits] 11 10 01 00 set _ nelc= figure 16-6 resolution vs. set_osr[2:0] and set_nelc[2:0] set_nelc set_os r [2:0] 00 01 10 11 000 6 7 8 9 001 8 9 10 11 010 10 11 12 13 011 12 13 14 15 100 14 15 16 16 101 16 16 16 16 110 16 16 16 16 111 16 16 16 16 (shaded area: resolution truncated to 16 bits due to output register size regacout[15:0] ) table 16-22 resolution vs. set_osr[2:0] and set_nelc[1:0] settings using look-up table 16-22 or the graph plotted in figure 16-6, resolution can be set between 6 and 16 bits. notice that, because of 16-bit register use for the adc output, practical resolution is limited to
16-16 d0304-60 datasheet xe88lc01 / 01a 16 bits , i.e. n 16. even if the resolution is truncated to 16 bit by the output register size, it may make sense to set osr and n elconv to higher values in order to reduce the influence of the thermal noise in the pga (see section 16.8.4). 16.7.6 conversion time & throughput as explained using figure 16-5, conversion time is given by: s elconv conv f osr n t / ) 1 ) 1 ( ( + + ? = (s) (eq. 16) and throughput is then simply 1/ t conv . for example, consider an over-sampling ratio of 256, 2 elementary conversions, and a sampling frequency of 500khz ( set_osr = "101", set_nelc = "01", f rc = 2mhz, and fin = "00"). in this case, using table 16-2 3, the conversion time is 515 sampling periods, or 1.03ms. this corresponds to a throughput of 971hz in continuous-time mode. the plot of figure 16-7 illustrates the classic trade-o ff between resolution and conversion time. set_nelc[1:0] set_osr [2:0] 00 01 10 11 000 10 19 37 73 001 18 35 69 137 010 34 67 133 265 011 66 131 261 521 100 130 259 517 1033 101 258 515 1029 2057 110 514 1027 2053 4105 111 1026 2051 4101 8201 table 16-23 normalized conversion time ( t conv ? f s ) vs. set_osr[2:0] and set_nelc[1:0] (normalized to sampling period 1/ f s ) 4.0 6.0 8.0 10.0 12.0 14.0 16.0 10.0 100.0 1000.0 10000.0 normalized conversion time - t conv *f s [-] resolution - n [bits] 00 set_nelc 01 10 11 figure 16-7 resolution vs. normalized conversion time for different set_nelc[1:0] 16.7.7 output code format the adc output code is a 16-bit word in two' s complement format (see table 16-24). for input voltages outside the range, the output code is saturat ed to the closest full-scale value (i.e. 0x7fff or 0x8000). for resolutions smaller than 16 bits, the non-si gnificant bits are forced to the values shown in table 16-25. the output code, expressed in lsbs, corresponds to:
16-17 d0304-60 datasheet xe88lc01 / 01a osr osr v v out ref adc in adc 1 2 , 16 + ? ? = (lsb) (eq.17) recalling equation eq. 9, this can be rewritten as: ? ? ? ? ? ? ? ? ? ? ? ? = in ref tot tot ref in adc v v gdoff gd v v out 16 2 osr osr 1 + ? (lsb) (eq. 18) where, from eq. 10 and eq. 11, the total pga gain and offset are respectively: 1 2 3 gd gd gd gd tot ? ? = (v/v) and: 2 3 3 gdoff gd gdoff gdoff tot ? + = (v/v) adc input voltage v in,adc % of full scale (fs) output in lsbs output code in hex +2.49505v +0.5 ? fs +2 15 -1 =+32'767 7fff +2.49497v ... +2 15 -2 =+32'766 7ffe ... ... ... ... +76.145 v ... +1 0001 0v 0 0 0000 -76.145 v ... -1 ffff ... ... ... ... -2.49505v ... -2 15 -1 =-32'767 8001 -2.49513v -0.5 ? fs -2 15 =-32'768 8000 table 16-24. basic adc re lationships (example for: v ref = 5v, osr = 512, n = 16 bits) set_os r [2:0] set_nelc = 00 set_nelc = 01 set_nelc = 10 set_nelc = 11 000 1000000000 100000000 10000000 1000000 001 10000000 1000000 100000 10000 010 100000 10000 1000 100 011 1000 100 10 1 100 10 1 - - 101 - - - - 110 - - - - 111 - - - - table 16-25. last forced lsbs in conversion output registers for resolution settings smaller than 16 bits ( n < 16) ( regacoutmsb[7:0] & regacoutlsb[7:0] )
16-18 d0304-60 datasheet xe88lc01 / 01a the equivalent lsb size at the input of the pga chain is: 1 2 1 + ? ? = osr osr gd v lsb tot ref n (v) (eq. 19) notice that the input voltage v in,adc of the adc must satisfy the condition: 1 ) ( 2 1 , + ? ? ? osr osr v v v refn refp adc in (v) (eq. 20) to remain within the adc input range. 16.7.8 power saving modes during low-speed operation, the bias current in the pgas and adc can be programmed to save power using the control words ib_amp_pga[1:0] and ib_amp_adc[1:0] (see table 16-26). if the system is idle, the pgas and adc can even be dis abled, thus, reducing power consumption to its minimum. this can considerably improve battery lifetime. ib_amp_adc [1:0] ib_amp_pga [1:0] adc bias current pga bias current max. f s [khz] 00 01 10 11 x 1/4 ? i adc 1/2 ? i adc 3/4 ? i adc i adc x 62.5 125 250 500 x 00 01 10 11 x 1/4 ? i pga 1/2 ? i pga 3/4 ? i pga i pga 62.5 125 250 500 table 16-26. adc & pga power saving modes and maximum sampling frequency 16.8 specifications and measured curves this section presents measurement results for the acquisition chain. a summary table with circuit specifications and measured curves are given. 16.8.1 default settings unless otherwise specified, the meas urement conditions are the following: ? temperature t a = +25c ? v dd = +5v, gnd = 0v, v ref = +5v, v in = 0v ? rc frequency f rc = 2mhz, sampling frequency f s = 500khz ? offsets gdoff 2 = gdoff 3 = 0 ? power operation: normal ( ib_amp_adc[1:0] = ib_amp_pga[1:0] = '11') ? resolution: for n = 12 bits: osr = 32 and n elconv = 4 for n = 16 bits: osr = 512 and n elconv = 2
16-19 d0304-60 datasheet xe88lc01 / 01a 16.8.2 specifications unless otherwise specified: temperature t a = +25c, v dd = +5v, gnd = 0v, v ref = +5v, v in = 0v, rc frequency f rc = 2mhz, sampling frequency f s = 500khz, overall pga gain gd tot = 1, offsets gdoff 2 = gdoff 3 = 0. power operation: normal ( ib_amp_adc[1:0] = ib_amp_pga[1:0] = '11'). for resolution n = 12 bits: osr = 32 and n elconv = 4. for resolution n = 16 bits: osr = 512 and n elconv = 2. value parameter min typ max units comments/conditions analog input characteristics differential input voltage ranges v in = (v inp - v inn ) reference voltage range v ref = (v refp ? v refn ) -2.42 -24.2 -2.42 +2.42 +24.2 +2.42 v dd v mv mv v gain = 1, osr = 32 (note 1) gain = 100, osr = 32 gain = 1000, osr = 32 programmable gain amplifiers (pga) total pga gain, gd tot pga1 gain, gd 1 pga2 gain, gd 2 pga3 gain, gd 3 gain setting precision (each stage) gain temperature dependence offset pga2 offset, gdoff 2 pga3 offset, gdoff 3 offset setting precision (pga2 or 3) offset temperature dependence input impedance pga1 pga2, pga3 output rms noise pga1 pga2 pga3 0.5 1 1 0 -3 -1 -127/12 -3 1500 150 150 0.5 5 0.5 5 205 340 365 1000 10 10 127/12 +3 +1 +127/12 +3 v/v v/v v/v v/v % ppm/c v/v v/v % ppm/c k ? k ? k ? v v v see table 16-14 see table 16-15 step=1/12 v/v, see table 16-17 step=0.2 v/v, see table 16-16 step=1/12 v/v, see table 16-18 (note 2) pga1 gain = 1 (note 3) pga1 gain = 10 (note 3) maximal gain (note 3) (note 4) (note 5) (note 6) adc static performance resolution, n no missing codes gain error offset error integral non-linearity, inl resolution n = 16 bits differential non-linearity, dnl resolution n = 16 bits power supply rejection ratio, psrr 6 0.15 1 1.0 0.5 78 72 16 bits % of fs lsb lsb lsb db db (note 7) (note 8) (note 9) n = 16 bits (note 10) (note 11) (note 12) v dd = 5v 0.3v (note 13) v dd = 3v 0.3v (note 13) dynamic performance sampling frequency, f s conversion time, t conv throughput rate (continuous mode), 1/t conv nbr of initialization cycles, n init nbr of end conversion cycles, n end pga stabilization delay 3 0 0 133 1027 3.76 0.49 osr 2 5 khz cycles/f s cycles/f s ksps ksps cycles cycles cycles n = 12 bits (note 14) n = 16 bits (note 14) n = 12 bits, f s = 500khz n = 16 bits, f s = 500khz (note 15) digital output adc output data coding binary two?s complement see table 16-24 and table 16-25
16-20 d0304-60 datasheet xe88lc01 / 01a specifications (cont?d) value parameter min typ max units comments/conditions power supply voltage supply range, v dd analog quiescent current consumption, total (i q ) adc only pga1 pga2 pga3 analog power dissipation normal power mode 3/4 power reduction mode 1/2 power reduction mode 1/4 power reduction mode +2.4 +5 720/620 250/190 165/150 130/120 175/160 3.6/1.9 2.7/1.4 1.8/0.9 0.9/0.5 +5.5 v a a a a a mw mw mw mw only acquisition chain v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v v dd = 5v/3v all pgas & adc active v dd = 5v/3v (note 16) v dd = 5v/3v (note 17) v dd = 5v/3v (note 18) v dd = 5v/3v (note 19) temperature specified range operating range -40 -40 +85 +125 c c notes: (1) gain defined as overall pga gain gd tot = gd 1 ? gd 2 ? gd 3 . maximum input voltage is given by: v in,max = (v ref /2) ? (osr/osr+1). (2) offset due to tolerance on gdoff 2 or gdoff 3 setting. for small intrinsic offset, use only adc and pga1. (3) measured with block connected to inputs through am ux block. normalized input sampling frequency for input impedance is f s = 512khz. this figure must be multiplied by 2 for f s = 256khz, 4 for f s = 128khz. input impedance is proportional to 1/ f s . (4) figure independent from pga1 gain and sampling frequency f s . see model of figure 16-18(a). see equation eq. 21 to calculate equivalent input noise. (5) figure independent on pga2 gain and sampling frequency f s . see model of figure 16-18(a). see equation eq. 21 to calculate equivalent input noise. (6) figure independent on pga3 gain and sampling frequency f s . see model of figure 16-18(a) and equation eq. 21 to calculate equivalent input noise. (7) resolution is given by n = 2 ? log2( osr ) + log2( n elconv ). osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (8) if a ramp signal is applied to the input, all di gital codes appear in the resulting adc output data. (9) gain error is defined as the amount of deviation betw een the ideal (theoretical) transfer function and the measured transfer function (with the offset error removed). (see figure 16-19) (10) offset error is defined as the output code erro r for a zero volt input (ideally, output code = 0). for 1 lsb offset, n elconv must be 2. (11) inl defined as the deviation of the dc transfer curve of each individual code from the best-fit straight line. this specification holds over the full scale. (12) dnl is defined as the difference (in lsb) between t he ideal (1 lsb) and measured c ode transitions for successive codes. (13) figures for gains = 1 to 100. psrr is defined as the amount of change in the adc output value as the power supply voltage changes. (14) conversion time is given by: t conv = ( n elconv ? ( osr + 1) + 1) / f s . osr can be set between 8 and 1024, in powers of 2. n elconv can be set to 1, 2, 4 or 8. (15) pgas are reset after each writing operation to registers regaccfg1-5 . the adc must be started after a pga or inputs common-mode stabilisation delay. this is done by wr iting bit start several cycles after pga settings modification or channel switching. delay between pga st art or input channel switching and adc start should be equivalent to osr (between 8 and 1024) number of cycles. this del ay does not apply to conversions made without the pgas. (16) nominal (maximum) bias currents in pgas and adc, i.e. ib_amp_pga[1:0] = ?11? and ib_amp_adc[1:0] = ?11?. (17) bias currents in pgas and adc set to 3/4 of nominal values, i.e. ib_amp_pga[1:0] = ?10?, ib_amp_adc[1:0] = ?10?. (18) bias currents in pgas and adc set to 1/2 of nominal values, i.e. ib_amp_pga[1:0] = ?01?, ib_amp_adc[1:0] = ?01?. (19) bias currents in pgas and adc set to 1/4 of nominal values, i.e. ib_amp_pga[1:0] = ?00?, ib_amp_adc[1:0] = ?00?.
16-21 d0304-60 datasheet xe88lc01 / 01a 16.8.3 linearity 16.8.3.1 integral non-linearity the integral non-linearity depends on the selected gain configuration. first of all, the non-linearity of the adc (all pga stages bypassed) is shown in figure 16-8. figure 16-8 integral non-linearity of the adc (pga disabled, reference voltage of 4.8v) the different pga stages have been designed to find the best compromise between the noise performance, the integral non-linearity and the power consumption. to obtain this, the first stage has the best noise performance and the third stage the be st linearity performance. for large input signals (small pga gains, i.e. up to about 50), the noise a dded by the pga is very small with respect to the input signal and the second and third stage of the pga should be used to get the best linearity. for small input signals (large gains, i.e. above 50), the noise level in the pga is important and the first stage of the pga should be used. the following figures give the non-linearity for different gain settings of the pga, selecting the appropriate stage to get the best noise and linearity performance. figure 16-9 shows the non-linearity when the third stage is used with a gain of 1. it is of course not very useful to use the pga with a gain of 1 unless it is used to compensate offset. by in creasing the gain, the integral non-linearity becomes even smaller since the signal in the amplifiers reduces. figure 16-10 shows the non-linearity for a gain of 2. figure 16-11 shows the non-linearity for a gain of 5. figure 16-12 shows the non-linearity for a gain of 10. by comparing these figures to figure 16-8, it can be seen that the third stage of the pga doe s not add significant integral non-linearity. figure 16-13 shows the non-linearity for a gain of 20 and figure 16-14 shows the non-linearity for a gain of 50. in both cases the pga2 is used at a gai n of 10 and the remaining gain is realized by the third stage. it can be seen again that the sec ond stage of the pga does not add significant non- linearity. for gains above 50, the first stage pga1 should be selected in stead of pga2. although the non- linearity in the first stage of the pga is larger than in stage 2 and 3, the gain in stage 3 is now sufficiently high so that the non-linearity of the first stage does become negligible as is shown in figure 16-15 for a gain of 100. therefor, the first stag e is preferred over the second stage since it has less noise.
16-22 d0304-60 datasheet xe88lc01 / 01a increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the first two stages. the signal is full sca le at the output of stage 3 and as shown in figure 16-9 to figure 16-12, this stage has very good linearity. figure 16-9 integral non-linearity of the adc and with gain of 1 (pga1 and pga2 disabled, pga3=1, reference voltage of 5v) figure 16-10 integral non-linearity of the adc and gain of 2 (pga1 and pga2 disabled, pga3=2 reference voltage of 5v)
16-23 d0304-60 datasheet xe88lc01 / 01a figure 16-11 integral non-linearity of the adc and gain of 5 (pga1 and pga2 disabled, pga3=5, reference voltage of 5v) figure 16-12 integral non-linearity of the adc and gain of 10 (pga1 and pga2 disabled, pga3=10, reference voltage of 5v) figure 16-13 integral non-linearity of the adc and gain of 20 (pga1 and pga2=10, pga3=2, reference voltage of 5v)
16-24 d0304-60 datasheet xe88lc01 / 01a figure 16-14 integral non-linearity of the adc and gain of 50 (pga1 disabled, pga2=10, pga3=5, reference voltage of 5v) figure 16-15 integral non-linearity of the adc and gain of 100 (pga1=10 and pga3=10, pga2 disabled, reference voltage of 5v) 16.8.3.2 differential non-linearity the differential non-linearity is generated by the a dc. the pga does not add differential non-linearity. figure 16-16 shows the differential non-linearity.
16-25 d0304-60 datasheet xe88lc01 / 01a figure 16-16 differential non-linearity of the adc converter. 16.8.4 noise ideally, a constant input voltage v in should result in a constant out put code. however, because of circuit noise, the output code may vary for a fixed input voltage. thus, a statistical analysis on the output code of 1200 conversions for a constant inpu t voltage was performed to derive the equivalent noise levels of pga1, pga2, and pga3. the extracted rms output noise of pga1, 2, and 3 are given in table 16-27: standard output deviation and ou tput rms noise voltage. figure 16-17 shows the distribution for the adc alone (pga 1, 2, and 3 bypassed). quantization noise is dominant in this case, and, thus, the adc thermal noise is below 16 bits. the simple noise model of figure 16-18(a) is used to estimate the equivalent input referred rms noise v n,in of the acquisition chain in the model of figur e 16-18(b). this is given by the relationship: ) ( )) /( ( )) /( ( ) / ( 2 3 2 1 3 2 2 1 2 2 1 1 2 , elconv n n n in n n osr gd gd gd v gd gd v gd v v ? ? ? + ? + = (v 2 rms) (eq. 21) where v n1 , v n2 , and v n3 are the output rms noise figures of table 16-27, gd 1 , gd 2 , and gd 3 are the pga gains of stages 1 to 3 respectively. as sh own in this equation, noise can be reduced by increasing osr and n elconv (increases the adc averaging effect, but reduces noise). parameter pga1 pga2 pga3 standard deviation at adc output (lsb) 0.85 1.4 1.5 output rms noise ( v) 1 205 (v n1 ) 340 (v n2 ) 365 (v n3 ) note: see noise model of figure 16-18 and equation eq. 21. table 16-27 pga noise measurements ( n = 16 bits, osr = 512, n elconv = 2, v ref = 5v)
16-26 d0304-60 datasheet xe88lc01 / 01a 0 20 40 60 80 -5 -4 -3 -2 -1 0 1 2 3 4 5 output code deviation from mean value [lsb] occurences [% of total samples] figure 16-17 adc noise (pga1, 2 & 3 bypassed, osr=512,n elconv =2) pga1 pga2 pga3 adc gd1 gd2 gd3 v n1 f s v n2 v n3 (a) pga1 pga2 pga3 adc gd1 gd2 gd3 v n,in f s (b) figure 16-18 (a) simple noise model for pgas and adc and (b) total input referred noise as an example, consider the system where: gd 2 = 10 ( gd 1 = 1; pga3 bypassed), osr = 512, n elconv = 2, v ref = 5v. in this case, the noise contribution v n1 of pga1 is dominant over that of pga2. using equation eq. 21, we get: v n,in = 6.4 v (rms) at the input of the acquisition chain, or, equivalently, 0.85 lsb at the output of the adc. c onsidering a 0.2v (rms) maximum signal amplitude, the signal-to-noise ratio is 90db. noise can also be reduced by implementing a softwar e filter. by making an average on a number of subsequent measurements, the appa rent noise is reduced the square root of the number of measurement used to make the average. 16.8.5 gain error and offset error gain error is defined as the amount of deviati on between the ideal transfer function (theoretical equation eq. 18) and the measured transfer func tion (with the offset error removed). the actual gain of the different stages can vary depen ding on the fabrication tole rances of the different elements. although these tolerances are specified to a maximum of 3%, they will be most of the time around 0.5%. moreover, the tolerances between the different stages are not correlated and the probability to get the maximal error in the same direction in all stages is very low. finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance.
16-27 d0304-60 datasheet xe88lc01 / 01a figure 16-19 shows gain error drift vs. temperature for different pga gains. the curves are expressed in % of full-scale range (fsr) normalized to 25c. offset error is defined as the output code error for a zero volt input (ideally, output code = 0). the offset of the adc and the pga1 st age are completely suppressed if n elconv > 1. the measured offset drift vs. temperature curves fo r different pga gains are depicted in figure 16-20. the output offset error, expressed in lsb for 16-bit setting, is normalized to 25c. notice that if the adc is used alone, the output offset error is below 1 lsb and has no drift. normalized to 25c -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 -50 -25 0 25 50 75 100 temperature [c] gain error [% of fsr] 1 5 20 100 figure 16-19 gain error vs. temperature for different pga gains normalized to 25c -40 -20 0 20 40 60 80 100 -50 -25 0 25 50 75 100 temperature [c] output offset error [lsb] 1 5 20 100 figure 16-20 offset error vs. temperature for different pga gains 16.8.6 power consumption figure 16-21 plots the variation of quiescent current consumption with supply voltage v dd , as well as the distribution between the 3 pga stages and the adc (see table 16-28). as shown in figure 16-22, if lower sampling frequency is used, the quiescent current consumption can be lowered by reducing the bias currents of the pgas and the adc with registers ib_amp_pga [1:0] and ib_amp_adc [1:0] . (in figure 16-22, ib_amp_pga/adc[1:0] = '11', '10', '00' for f s = 500, 250, 62.5khz respectively.)
16-28 d0304-60 datasheet xe88lc01 / 01a quiescent current consumption vs . temperature is depicted in figure 16-23, showing a relative increase of nearly 40% between -45 and +85c. figu re 16-24 shows the variati on of quiescent current consumption for different frequency settings of the internal rc oscillator. it can be seen that the quiescent current varies by about 20% between 100khz and 2mhz. 100 200 300 400 500 600 700 800 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage - v dda [v] quiescent current - i q [ a] no pgas, adc only pga1 + adc pga1 & 2 + adc pga1, 2 & 3 + adc figure 16-21 quiescent current consumption vs. supply voltage 100 200 300 400 500 600 700 800 2.53.03.54.04.55.05.5 supply voltage - v dda [v] quiescent current - i q [ a] 500khz sampling frequency f s : 250khz 62.5khz figure 16-22 quiescent current consumption vs. supply voltage for different sampling frequencies 500 550 600 650 700 750 800 850 900 -50 -25 0 25 50 75 100 125 temperature [c] quiescent current - i q [ a] -25 -20 -15 -10 -5 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature [c] relative quiescent current change i q / i q,25c [%] (a) (b) figure 16-23 (a) absolute and (b) relative change inquiescent current consumption vs. temperature
16-29 d0304-60 datasheet xe88lc01 / 01a supply adc pga1 pga2 pga3 total unit v dd = 5v 250 165 130 175 720 a v dd = 3v 190 150 120 160 620 a table 16-28 typical quiescent current distribu tions in acquisition chain (n = 16 bits, f s = 500khz) -20 -15 -10 -5 0 5 10 15 0 500 1000 1500 2000 2500 3000 3500 frequency - f rc [khz] relative quiescent current change ? i q / i q,2m hz [%] 500 550 600 650 700 750 800 850 0 500 1000 1500 2000 2500 3000 3500 frequency - f rc [khz] quiescent current - i q [ a] (a) (b) figure 16-24 (a) absolute and (b) relative change in quiescent curent consumption vs. rc oscillator frequency (all pgas active, v dd = 5v) 16.8.7 power supply rejection ratio figure 16-25 shows power supply reje ction ratio (psrr) at 3v and 5v supply voltage, and for various pga gains. psrr is defined as the ratio (in db) of voltage supply change (in v) to the change in the converter output (in v). psrr depends on both pga gain and supply voltage v dd . 60 65 70 75 80 85 90 95 100 105 1 5 10 20 100 pga gain [v/v] psrr [db] vdd=3v vdd=5v figure 16-25 power supply rejection ratio (psrr)
16-30 d0304-60 datasheet xe88lc01 / 01a supply gain = 1 gain =5 gain = 10 gain = 20 gain =100 unit v dd = 5v 79 78 100 99 97 db v dd = 3v 72 79 90 90 86 db table 16-29 psrr (n = 16 bits, v in = v ref = 2.5v, f s = 500khz) 16.9 application hints 16.9.1 input impedance the pgas of the acquisition chain employ switched-capacitor techniques. for this reason, while a conversion is done, the input impedance on the selected channel of the pgas is inversely proportional to the sampling frequency f s and to stage gain as given in equation 22. gain f hz z s in ? ? ? 9 10 768 (eq. 22) the input impedance observed is the input impedance of the first pga stage that is enabled or the input impedance of the adc if all three stages are disabled. pga1 (with a gain of 10), pga2 (with a gain of 10) and pga3 (with a gain of 10) each have a minimum input impedance of 150k ? at f s = 512khz (see specification table). larger input impedance can be obtained by reducing the gain and/or by reducing the sampling frequency. therefor, with a gain of 1 and a sampling frequency of 100khz, z in > 7.6m ? . the input impedance on channels that ar e not selected is very high (>100m ? ). 16.9.2 pga settling or input channel modifications pgas are reset after each writing operation to registers regaccfg1-5 . similarly, input channels are switched after modifications of amux[4:0] or vmux . to ensure precise conver sion, the adc must be started after a pga or inputs common-mode stabi lization delay. this is done by writing bit start several cycles after pga settings modification or ch annel switching. delay between pga start or input channel switching and adc start should be equivalent to osr (between 8 and 1024) number of cycles. this delay does not apply to conversions made without the pgas. if the adc is not settled within the specified period, there is most probably an input impedance problem (see previous section). 16.9.3 pga gain & offset, linearity and noise hereafter are a few design guidelines that sh ould be taken into account when using the zoomingadc ? : 1) keep in mind that increasing the overa ll pga gain, or "zooming" coefficient, improves linearity but degrades noise performance. 2) use the minimum number of pga stages necess ary to produce the desired gain ("zooming") and offset. bypass unnecessary pgas. 3) for high gains (>50), use pga stage 1. for low gains (<50) use stages 2 and 3.
16-31 d0304-60 datasheet xe88lc01 / 01a 4) for the lowest noise, set the highest possible gain on the first (front) pga stage used in the chain. for example, in an application where a gai n of 20 is needed, set the gain of pga2 to 10, set the gain of pga3 to 2. 4) for highest linearity and lowest noise perfor mance, bypass all pgas and use the adc alone (applications where no "zooming" is needed); i.e. set enable[3:0] = '0001'. 5) for low-noise applications where power consum ption is not a primary concern, maintain the largest bias currents in the pgas and in the adc; i.e. set ib_amp_pga[1:0] = ib_amp_adc[1:0] = '11'. 6) for lowest output offset error at the out put of the adc, bypass pga2 and pga3. indeed, pga2 and pga3 typically introduce an offset of about 5 to 10 lsb (16 bit) at their output. note, however, that the adc output offset is easily calibrated out by software. 16.9.4 frequency response the incremental adc is an over-sampled converte r with two main blocks: an analog modulator and a low-pass digital filter. the main function of the di gital filter is to remove the quantization noise introduced by the modulator. as shown in figure 16-26, this filter determines the frequency response of the transfer function between the output of the adc and the analog input v in . notice that the frequency axes are normalized to one elementary conversion period osr / f s . the plots of figure 16-26 also show that the frequency response change s with the number of elementary conversions n elconv performed. in particular, notches appear for n elconv 2. these notches occur at: elconv s notch n osr f i i f ? ? = ) ( (hz) for ) 1 ( ,..., 2 , 1 ? = elconv n i (eq. 23) and are repeated every f s / osr . information on the location of these notches is par ticularly useful when specific frequencies must be filtered out by the acquisition syst em. for example, consider a 5hz- bandwidth, 16-bit sensing system where 50hz line rejection is needed. using the above equation and the plots below, we set the 4th notch for n elconv = 4 to 50hz, i.e. 1.25 ? f s / osr = 50hz. the sampling frequency is then calculated as f s = 20.48khz for osr = 512. notice that this choice yiel ds also good attenuation of 50hz harmonics.
16-32 d0304-60 datasheet xe88lc01 / 01a 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 1 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 2 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 4 0 0.2 0.4 0.6 0.8 1 1.2 01234 normalized frequency - f *(osr/f s ) [-] normalized magnitude [-] n el c onv = 8 figure 16-26 frequency response: normalized magnitude vs. frequency for different n elconv 16.9.5 power reduction the zoomingadc? is particularly well suited for low-power applications. when very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to reduce power consumption as follows: 1) operate the acquisition chain with a reduced supply voltage v dd . 2) disable the pgas which are not used during analog-to-digital conversion with enable[3:0] . 3) disable all pgas and the adc when the syst em is idle and no conversion is performed. 4) use lower bias currents in the pgas and the adc using the control words ib_amp_pga[1:0] and ib_amp_adc[1:0] . (this reduces the maximum sampling frequency according to table 16-26.) 5) reduce internal rc oscillator frequency and/or sampling frequency. finally, remember that power reduct ion is typically traded off with reduced linearity, larger noise and slower maximum sampling speed.
17-1 vmult_ff - 1.0 ? 11 october 2002 d0304-60 datasheet xe88lc01/01a 17. vmult (voltage multiplier) 17.1 features 17-2 17.2 overview 17-2 17.3 control register 17-2 17.4 external component 17-2
17-2 d0304-60 datasheet xe88lc01/01a 17.1 features ? generates a voltage that is higher or equal to the supply voltage. ? can be easily enabled or disabled 17.2 overview the vmult block generates a voltage (called ?vmult?) t hat is higher or equal to the supply voltage. this output voltage is used in the acquisition chain. the voltage multiplier should be on (bit enable in regvmultcfg0 ) when using the acquisition chain or analog properties of the port b while vbat is bel ow 3v. if the multiplier is enabled, the external capacitor on the pin vmult is mandatory. the source clock of vmult is selected by fin[1:0] in regvmultcfg0 . it is strongly recommended to use the same settings as in the adc. 17.3 control register there is only one register in the vmult. tabl e 17-1 describes the bits in the register. pos. regvmultcfg0 rw reset function 2 enable rw 0 resetsystem enable of the vmult ?1? : enabled ?0? : disabled 1-0 fin rw 0 resetsystem system clock division factor ?00? : 1/2, ?01? : 1/4, ?10? : 1/16, ?11? : 1/64 table 17-1. regvmultcfg0 17.4 external component when the multiplier is enabled, a capacitor has to be connected to the vmult pin. if the multiplier is disabled, the pin may remain floating. min. max. note capacitor on vmult 1.0 3.0 nf
18-1 cnt_ff - 1.2 ? 14 march 2002 d0304-60 datasheet xe88lc01/01a 18 counters/timers/pwm 18.1 features 18-2 18.2 overview 18-2 18.3 register map 18-2 18.4 interrupts and events map 18-3 18.5 block schematic 18-4 18.6 general counter registers operation 18-4 18.7 clock selection 18-5 18.8 counter mode selection 18-5 18.9 counter / timer mode 18-6 18.10 pwm mode 18-8 18.11 capture function 18-9
18-2 d0304-60 datasheet xe88lc01/01a 18.1 features ? 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules ? each with 4 possible clock sources ? up/down counter modes ? interrupt and event generation ? capture function (internal or external source) ? rising, falling or both edge of capture signal ? pa[3:0] can be used as clock inputs (debounced or direct) ? 2 x 8 bits pwm or 2 x 16 bits pwm ? pwm resolution of 8, 10, 12, 14 or 16 bits ? complex mode combinations are possibl e between counter, capture and pwm modes 18.2 overview countera and counterb are 8-bit counters and can be combined to form a 16-bit counter. counterc and counterd exhibit the same features. the counters can also be used to generate two pwm outputs on pb[0] and pb[1]. in pwm mode one can generate pwm functions with 8, 10, 12, 14 or 16 bit wide counters. the counters a and b can be captured by events on an in ternal or an external signal. the capture can be performed on both 8-bit counters running individua lly on two different clock sources or on both counters chained to form a 16-bit counter. in any case, the same capture signal is used for both counters. when the counters a and b are not chained, they c an be used in several configurations: a and b as counters, a and b as captured counters, a as pw m and b as counter, a as pwm and b as captured counter. when the counters c and d are not c hained, they can be used either both as counters or counter c as pwm and counter d as counter. 18.3 register map bit regcnta rw reset function 7-0 countera r xxxxxxxx 8-bits counter value 7-0 countera w xxxxxxxx 8-bits com parison value table 18-1. regcnta bit regcntb rw reset function 7-0 counterb r xxxxxxxx 8-bits counter value 7-0 counterb w xxxxxxxx 8-bits com parison value table 18-2. regcntb note: when writing to regcnta or regcntb , the processor writes the counter comparison values. when reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit regcntc rw reset function 7-0 counterc r xxxxxxxx 8-bits counter value 7-0 counterc w xxxxxxxx 8-bits com parison value table 18-3. regcntc
18-3 d0304-60 datasheet xe88lc01/01a bit regcntd rw reset function 7-0 counterd r xxxxxxxx 8-bits counter value 7-0 counterd w xxxxxxxx 8-bits com parison value table 18-4. regcntd note: when writing regcntc or regcntd , the processor writes the counter comparison values. when reading these locations, the processor reads back the actual counter value. bit regcntctrlck rw reset function 7-6 cntdcksel(1:0) rw xx counter d clock selection 5-4 cntccksel(1:0) rw xx counter c clock selection 3-2 cntbcksel(1:0) rw xx counter b clock selection 1-0 cntacksel(1:0) rw xx counter a clock selection table 18-5. regcntctrlck bit regcntconfig1 rw reset function 7 cntddownup rw x counter d up or down counting (0=down) 6 cntcdownup rw x counter c up or down counting (0=down) 5 cntbdownup rw x counter b up or down counting (0=down) 4 cntadownup rw x counter a up or down counting (0=down) 3 cascadecd rw x cascade counter c & d (1=cascade) 2 cascadeab rw x cascade counter a & b (1=cascade) 1 cntpwm1 rw 0 resetsystem activate pwm1 on counter c or c+d (pb(1)) 0 cntpwm0 rw 0 resetsystem activate pwm0 on counter a or a+b (pb(0)) table 18-6. regcntconfig1 bit regcntconfig2 rw reset function 7-6 capsel(1:0) rw 00 resetsystem capture source selection 5-4 capfunc(1:0) rw 00 resetsystem capture function 3-2 pwm1size(1:0) rw xx pwm1 size selection 1-0 pwm0size(1:0) rw xx pwm0 size selection table 18-7. regcntconfig2 bit regcnton rw reset function 7-4 -- r 0000 reserved 3 cntdenable rw 0 resetsystem enable counter d 2 cntcenable rw 0 resetsystem enable counter c 1 cntbenable rw 0 resetsystem enable counter b 0 cntaenable rw 0 resetsystem enable counter a table 18-8. regcnton 18.4 interrupts and events map interrupt source mapping in the interrupt manager mapping in the event manager irqa regirqhigh(4) regevn(7) irqb regirqlow(5) regevn(3) irqc regirqhigh(3) regevn(6) irqd regirqlow(4) regevn(2) table 18-9. interrupt and event mapping.
18-4 d0304-60 datasheet xe88lc01/01a 18.5 block schematic pb(0) capture ck32k ck1k pa(0) regcnta (write) counter a pa(2) regcntc (write) counter c regcntd (write) counter d regcntb (write) counter b pa(1) pa(3) ck128 ckrcext/4 ckrcext ck1k ck32k pwm pb(1) regcnta (read) regcntb (read) regcntc (read) regcntd (read) figure 18-1: counters/timers block schematic 18.6 general counter registers operation counters are enabled by cntaenable , cntbenable , cntcenable , and cntdenable in regcnton . to stop the counter x, cnt x enable must be reset. to start the counter x, cnt x enable must be set. when counters are cascaded, cntaenable and cntcenable also control respectively the counters b and d. in the control registers, all regist ers must be written in this order: regcntctrlck , regcntconfig1 , regcntconfig2 and all regcntx because several bits have no default values at reset. all counters have a corresponding 8-bit read/write register: regcnta , regcntb , regcntc , and regcntd . when read, these registers contain the count er value (or the captured counter value). when written, they modify t he counter comparison values. for a correct acquisition of the counter va lue, use one of the three following methods: 1) stop the concerned counter, perform the read operation and restart the counter. while stopped, the counter content is frozen and the counter does not take into account the clock edges delivered on the external pin.
18-5 d0304-60 datasheet xe88lc01/01a 2) for slow operating counters (typically at least 8 times slower than the cpu clock), oversample the counter content and perform a majority operation on the consecutive read results to select the correct actual content of the counter. 3) use the capture mechanism. when a value is written into the counter register while the counter is in counter mode, both the comparison value is updated and the counter value is m odified. in upcount mode, the register value is reset to zero. in downcount mode, the comparis on value is loaded into the counter. due to the synchronization mechanism between the processor clock domain and the external clock source domain, this modification of the counter val ue can be postponed until the counter is enabled and it receives it?s first valid clock edge. in the pwm mode, the counter value is not modifi ed by the write operation in the counter register. changing the counter mode, does not update the c ounter value (no load in downcount mode). 18.7 clock selection the clock source for each counter can be individually selected by writing the appropriate value in the register regcntctrlck . table 18-10 gives the correspondence between the bi nary codes used for the configuration bits cntacksel(1:0) , cntbcksel(1:0), cntccksel(1:0) or cntdcksel(1:0) and the clock source selected respectively for the counters a, b, c or d. clock source for cnt x cksel(1:0) countera counterb counterc counterd 11 ck128 10 ckrc/4 ck1k 01 ckrc ck32k 00 pa(0) pa(1) pa(2) pa(3) table 18 - 10: clock sources for counters a, b, c and d the ckrc clock is the rc oscillator. the clocks bel ow 32khz can be derived from the rc oscillator or the crystal oscillator (see the documentation of the cl ock block). a separate external clock source can be delivered on port a for each individual counter. the external clock sources can be debounced or not by setting the port a configuration registers. the clock source can be changed only when the counter is stopped. 18.8 counter mode selection each counter can work in one of the following modes: 1) counter, downcount & upcount 2) captured counter, downcount & upcount (only counters a&b) 3) pwm, downcount the counters a and b or c and d can be cascaded or not. in cascaded mode, a and c are the lsb counters while b and d are the msb counters. table 18-11 shows the different operation modes of the counters a and b as a function of the mode control bits. for all counter modes, the source of t he down or upcount selection is given (either the bit
18-6 d0304-60 datasheet xe88lc01/01a cntadownup or the bit cntbdownup ). also, the mapping of the inte rrupt sources irqa and irqb and the pwm output on pb(0) in thes e different modes is shown. cascadeab countpwm0 capfunc(1:0) counter a mode counter b mode irqa source irqb source pb(0) function 0 0 00 counter 8b downup: a counter 8b downup: b counter a counter b pb(0) 1 0 00 counter 16b ab downup: a counter ab - pb(0) 0 1 00 pwm 8b down counter 8b down - counter b pwm a 1 1 00 pwm 10 ? 16b ab down - - pwm ab 0 0 1x or x1 captured counter 8b downup: a captured counter 8b downup: b capture a capture b pb(0) 1 0 1x or x1 captured counter 16b ab downup: a capture ab capture ab pb(0) 0 1 1x or x1 pwm 8b down captured counter 8b downup: b must not be used capture b pwm a table 18 - 11: operating modes of the counters a and b table 18-12 shows the different operation modes of the counters c and d as a function of the mode control bits. for all counter modes, the source of the down or upcount se lection is given (either the bit cntcdownup or the bit cntddownup ). the mapping of the interrupt sources irqc and irqd and the pwm output on pb(1) in these diffe rent modes is also shown. the switching between different modes must be done while the concerned counters are stopped. while switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change. cascadecd countpwm1 counter c mode counter d mode irqc source irqd source pb(1) function 0 0 counter 8b downup: c counter 8b downup: d counter c counter d pb(1) 1 0 counter 16b cd downup: c counter cd - pb(1) 0 1 pwm 8b down counter 8b down - counter d pwm c 1 1 pwm 10 ? 16b cd down - - pwm cd table 18 - 12: operating modes of the counters c and d 18.9 counter / timer mode the counters in counter / timer mode are genera lly used to generate interrupts after a predefined number of clock periods applied on the counter clock input. each counter can be set individually either in upcount mode by setting cnt x downup in the register regcntconfig1 or in downcount mode by resetting this bit. counters a and b can be cascaded to
18-7 d0304-60 datasheet xe88lc01/01a behave as a 16 bit counter by setting cascadeab in the regcntconfig1 register. counters c and d can be cascaded by setting cascadecd . when cascaded, the up/down c ount modes of the counters b and d are defined respectively by the up/dow n count modes set for the counters a and c. when in upcount mode, the counter will start increment ing from zero up to the target value which has been written in the corresponding regcnt x register(s). when the count er content is equal to the target value, an interrupt is generated at the next falling edge of counter clock. then the counter is loaded again with the zero value at the next rising edge of counter clock (figure 18-2). when in downcount mode, the counter will start decre menting from the initial load value which has been written in the corresponding regcnt x register(s) down to the zero value. once the counter content is equal to zero, an interrupt is generated at the next falling edge of counter clock. then the counter is loaded again with the load value at t he next rising edge of counter clock (figure 18-2). be careful to select the counter mode (no captur e, not pwm, specify cascaded or not and up or down counting mode) before writing any target or load value to the regcnt x register(s). this ensures that the counter will start from the correct initia l value. when counters are cascaded, both counter registers must be written to ens ure that both cascaded counters will start from the correct initial values. the stopping and consecutive starting of a counter in counter mode without a target or load value write operation in between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it?s target value (upcount). this interrupt is additional to the interrupt which has already been generated when the counter r eached the zero or the target value. d own coun ti ng clock counter x regcntx _ r xx 321032103210 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable up coun ti ng clock counter x regcntx _ r xx0 12301230123 regcntx _ w xx 3 write regcntx cntxdownup irqx cntxenable figure 18-2. up and down count interrupt generation.
18-8 d0304-60 datasheet xe88lc01/01a 18.10 pwm mode the counters can generate pwm signals (pulse widt h modulation) on the port b outputs pb(0) and pb(1). the pwm mode is selected by setting cntpwm1 and cntpwm0 in the regcntconfig1 register. see table 18-11 and table 18-12 for an exact description of how the setting of cntpwm1 and cntpwm0 affects the operating mode of the c ounters a, b, c and d according to the other configuration settings. when cntpwm0 is enabled, the pwma or pwmab output va lue overrides the value set in bit 0 of regpbout in the port b peripheral. when cntpwm1 is enabled, the pwmc or pwmcd output value overrides the value set in bit 1 of regpbout . the corresponding ports (0 and/or 1) of port b must be set in digital mode and as output and either open drain or not and pull up or not through a proper setting of the control registers of the port b. counters in pwm mode always count down, the cnt x downup bit setting must be reset. no interrupts and events are generated by the counters which are in pwm mode. counters do count circularly: they restart at the maximal va lue (either 0xff when not cascaded or 0xffff when cascaded) when respectively an underflow condition occurs in the counting. the internal pwm signals are low as long as t he counter contents are higher than the pwm code values written in the regcnt x registers. they are high when t he counter contents are smaller or equal to these pwm code values. the pwm resolution is always 8 bits when the counters used for the pwm signal generation are not cascaded. pwm0size(1:0) and pwm1size(1:0) in the regcntconfig2 register are used to set the pwm resolution for the counters a and b or c and d respectively when they are in cascaded mode. the different possible resolutions in cascaded mode are shown in table 18-13. choosing a 16 bit pwm code higher than the maximum value that can be represented by the number of bits chosen for the resolution, results in a pwm output which is always tied to 1. pwmxsize(1:0) resolution 11 16 bits 10 14 bits 01 12 bits 00 10 bits table 18 - 13 : resolution selection in cascaded pwm mode small pwm code large pwm code t per t hlarge t llarge t hsmall t lsmall figure 18-3: pwm modulation examples the period of the pwm signal is given by the formula:
18-9 d0304-60 datasheet xe88lc01/01a ckcnt resolution f tper 2 = the duty cycle ratio dcr of the pwm signal is defined as: tper th dcr = dcr can be selected between 0 % and 100 * 2 1 2 resolution resolution ? %. dcr in % in function of the regcntx c ontent(s) is given by the relation: resolution dcr 2 regcntx * 100 = 18.11 capture function the 16-bit capture register is provided to fac ilitate frequency measurements. it provides a safe reading mechanism for the counters a and b when t hey are running. when the capture function is active, the processor does not read anymore the counters a and b directly, but instead reads shadow registers located in the capture block. an in terrupt is generated after a capture condition has been met when the shadow register content is updated. t he capture condition is user defined by selecting either internal capture signal sources derived from t he prescaler or from the external pa(2) or pa(3) ports. both counters use the same capture condition. when the capture function is active, the a and b counters must be written with the value 0xff and can either upcount or downcount. they do count circularly: they restart at zero or at the maximal value (either 0xff when not cascaded or 0xffff when ca scaded) when respectively an overflow or an underflow condition occurs in the counting. capfunc(1:0) in register regcntconfig2 determines if the capture function is enabled or not and selects which edges of the capture signal source are valid for the capture operation. the source of the capture signal can be selected by setting capsel(1:0) in the regcntconfig2 register. for all sources, rising, falling or both edge sensitivity can be selected. table 18-14 shows the capture condition as a function of the setti ng of these configuration bits. capsel(1:0) selected capture signal capfunc selected condition capture condition 11 1 k 00 01 10 11 capture disabled rising edge falling edge both edges - 1 k rising edge 1 k falling edge 1 k both edges 10 32 k 00 01 10 11 capture disabled rising edge falling edge both edges - 32 k rising edge 32 k falling edge 32 k both edges 01 pa3 00 01 10 11 capture disabled rising edge falling edge both edges - pa3 rising edge pa3 falling edge pa3 both edges 00 pa2 00 01 10 11 capture disabled rising edge falling edge both edges - pa2 rising edge pa2 falling edge pa2 both edges table 18 - 14: capture condition selection
18-10 d0304-60 datasheet xe88lc01/01a capfunc(1:0) and capsel(1:0) can be modified only when the c ounters are stopped otherwise data may be corrupted during one counter clock cycle. due to the synchronization mechanism of t he shadow registers and depending on the frequency ratio between the capture and counter clocks, the in terrupts may be generated one or only two counter clock pulses after the effective capture condi tion occurred. when the counters a and b are not cascaded and do not operate on the same clock, the inte rruptions on irqa and irqb which inform that the capture condition was met, may appear at different moments. in this case, the processor should read the shadow register associated to a counter only if the interruption related to this counter has been detected. it must be noted that when counters a and b are cascaded, the capture might happen at different cycles for the a and b registers. this is due to the asynchronous relationship between counter and capture clock and to the fact that the capture condition detection is independent for a and b counters.
19-1 vld_ff - 1.0 ? 24 september 2002 d0304-60 datasheet xe88lc01/01a 19 vld (voltage level detector) 19.1 features 19-2 19.2 overview 19-2 19.3 register map 19-2 19.4 interrupt map 19-2 19.5 vld operation 19-2
19-2 d0304-60 datasheet xe88lc01/01a 19.1 features ? can be switched off, on or simu ltaneously with cpu activities ? generates an interrupt if power s upply is below a pre-determined level 19.2 overview the voltage level detector monitors the state of the system battery. it returns a logical high value (an interrupt) in the status register if the suppli ed voltage drops below the user defined level (vsb). 19.3 register map there are two registers in the vld, namely regvldctrl and regvldstat . table 19-1 shows the mapping of control bits and functionality of regvldctrl while table 19-2 describes that for regvldstat . pos. regvldctrl rw reset function 7-4 -- r 0000 reserved 3 vldrange r w 0 resetsystem vld detection voltage range for vldtune = ?011?: 0 : 1.3v 1 : 2.55v 2-0 vldtune[2:0] r w 000 resetsystem vld tuning: 000 : +19 % 111 : -18 % table 19-1 : regvldctrl pos. regvldstat rw reset function 7-3 -- r 00000 reserved 2 vldresult r 0 resetsystem is 1 when battery voltage is below the detection voltage 1 vldvalid r 0 resetsystem indicates when vldresult can be read 0 vlden r w 0 resetsystem vld enable table 19-2 : regvldstat 19.4 interrupt map interrupt source mapping in the interrupt manager irqvld regirqmid(2) table 19-3 : interrupt map 19.5 vld operation the vld is controlled by vldrange , vldtune and vlden . vldrange selects the voltage range to be detected, while vldtune is used to fine-tune this voltage level in 8 steps. vlden is used to enable (disable) the vld with a 1(0) value respectively. disabled, the block will dissipate no power.
19-3 d0304-60 datasheet xe88lc01/01a symbol description min typ max unit comments trimming values: note 1 vldrange vldtune 1.53 0 000 1.44 0 001 1.36 0 010 1.29 0 011 1.22 0 100 1.16 0 101 1.11 0 110 1.06 0 111 3.06 1 000 2.88 1 001 2.72 1 010 2.57 1 011 2.44 1 100 2.33 1 101 2.22 1 110 vth threshold voltage 2.13 v 1 111 t eom duration of measurement 2.0 2.5 ms note 2 t pw minimum pulse width detected 875 1350 us note 2 table 19-4: voltage level detector operation note 1: absolute precision of the threshold voltage is 10%. note 2: this timing is respected in case the inte rnal rc or crystal oscillators are enabled to start the voltage level detection, the user sets bit vlden . the measurement is started. after 2ms, the bit vldvalid is set to indicate that the measurem ent results are valid. from that time on, as long as the vld is enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. one can also poll the vld and monito r the actual measurement result by reading the vldresult bit of the regvldstat . this result is only valid as long as the vldvalid bit is ?1?. an interrupt is generated on each rising edge of vldresult .
20-1 lc01 - 1.0 ? 11 october 2002 d0304-60 datasheet xe88lc01 / 01a 20 physical dimensions contents 20.1 qfp type package 20-2
20-2 d0304-60 datasheet xe88lc01 / 01a 20.1 qfp type package the qfp package dimensions are given in figure 20-1 and table 20-1. the dimensions conform to jedec ms-026 rev. c. figure 20-1. qfp type package package a mm b mm c mm d mm e mm f mm g mm lqfp-44 10.0 12.0 1.4 0.10 0.37 0.8 table 20-1. qfp package dimensions ? xemics 2003 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. t he information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher fo r any consequence of its use. p ublication thereof does not con vey nor imply any license under patent or other industria l or intellectual property rights. xemics products are not designed, intended, authoriz ed or warranted to be suitable for use in life- support applications, devices or sy stems or other critical applications . inclusion of xemics products in such applications is understood to be undert aken solely at the customer?s own risk. should a customer purchase or use xemics products for any such unauthorized application, the customer shall indemnify and hold xemics and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and a ttorney fees which could arise.

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